CFET-Based 8T SRAM Bit Cell for High-Density Dual-Port SoC
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Solution Overview
Problem
The demand for higher performance two-port SRAM in advanced system-on-chips (SoCs) is increasing, but current 8-transistor dual-port SRAM bit-cells introduce significant area overhead, typically 1.5 times larger than 6-transistor single-port SRAM bit-cells, making them less suitable for high-density applications.
Innovation Solution
A CFET-based 8T SRAM bit cell design is proposed, utilizing complementary field-effect transistors (CFETs) with a layout that stacks NMOS and PMOS devices vertically, allowing for a dual-port implementation with a footprint ratio comparable to single-port bit-cells, achieved by using CFET devices with shared gates and separate control for pass-gates via word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 8-transistor dual-port SRAM bit-cell is used, then dual-port performance is improved, but area overhead increases significantly (1.5 times larger than 6T single-port)
Solution Approach 1:
The patent transitions from planar device arrangement to vertical stacking by introducing CFET (complementary field-effect transistor) technology. NMOS and PMOS devices are stacked vertically in three dimensions, allowing the dual-port bit-cell to achieve density comparable to single-port designs by utilizing the vertical dimension for device placement rather than expanding horizontally.
Solution Approach 2:
The CFET structure enables each stacked device pair to serve multiple functions simultaneously. The shared gate structure and vertical stacking allow the same physical space to accommodate both the storage function and the dual-port access function, making the bit-cell structure universally applicable for high-density dual-port memory implementations.
2Area of stationary object
If 6T single-port bit-cell is used, then area footprint is reduced, but dual-port capability is lost
Solution Approach 1:
By stacking CFET devices vertically, the patent enables dual-port capability within the same footprint as single-port designs. The vertical arrangement of NMOS and PMOS devices creates space for additional access transistors and word line connections without increasing the lateral footprint, thus maintaining compactness while gaining dual-port functionality.
Solution Approach 2:
The patent merges the access transistors for both ports with the storage transistor structure in the vertical CFET stack. The shared gate and stacked configuration allow both port A and port B access transistors to be integrated into the same vertical column, combining multiple functions into a unified structure that achieves dual-port capability without additional footprint.
Data Source
AI summary
A static random access memory (SRAM) device includes a plurality of bit cells, each bit-cell including a first half-cell and a second half-cell, each half-cell including a first and a second complementary field-effect transistor (CFET) device. Each CFET device includes a bottom device and a top device stacked on top of the bottom device. The first CFET device includes a common gate shared by the bottom device and the top device and is configured as an inverter cross-coupled to the inverter of the other half-cell. The bottom device of the second CFET device is configured as a first pass-gate for a first port of the half-cell. The top device of the second CFET device is configured as a second pass-gate for a second port of the half-cell.