Split Gate Memory Cell Sidewall Spacer Self-Aligned Process
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Solution Overview
Problem
Existing split-gate memory cells are difficult to miniaturize due to the need for separate masks to define the control and select gates, limiting their integration and programming efficiency.
Innovation Solution
A self-aligned process is used to form sublithographic feature size control and select gates without a mask, by extending a material above the gate stack and forming a sidewall spacer that splits the gate stack into two portions, allowing for reduced cell size and improved programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate masks are used to define control and select gates in known split-gate memory cells, then the gates can be properly formed and function, but the cell size cannot be reduced and manufacturing complexity increases
Solution Approach 1:
The patent combines the control gate and select gate formation into a single self-aligned process. A unified gate structure is formed first, then a sidewall spacer is deposited and patterned to simultaneously define both gates in one etching step, eliminating the need for separate masks and reducing manufacturing complexity while maintaining precise gate definition
Solution Approach 2:
The sidewall spacer acts as a self-aligned mask that automatically positions the etching boundaries for both control and select gates. The spacer's position is determined by the gate structure itself, creating a self-aligned process that eliminates the need for external mask alignment and reduces processing steps
2Manufacturing precision
If separate masks are used for control and select gates, then proper gate formation is achieved, but integration density decreases
Solution Approach 1:
The sidewall spacer provides self-aligned separation between control and select gates, with the spacer position automatically determined by the gate structure. This eliminates the need for additional mask alignment steps and allows for tighter gate spacing, reducing the overall cell area while maintaining precise gate separation
Solution Approach 2:
The patent introduces a vertical dimension by forming a sidewall spacer that extends upward from the substrate. This vertical structure serves as the separating element between gates, replacing what would traditionally require horizontal mask patterns and allowing for more compact planar cell layout
Data Source
AI summary
A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by at least a gap length. Etching the bitcell stack, selective to the spacers, forms a gap that splits the bitcell stack into first and second gates which together form the split gate bitcell stack. A storage portion of bitcell stack is also etched, wherein etching extends the gap and separates the corresponding layer into first and second separate regions, the extended gap being devoid of charge storage material. Dielectric material is deposited over the gap and etched back to expose a top surface of the sacrificial layer, which is thereafter removed to expose sidewalls of the split gate bitcell stack.