Vertical FET Gate Length Uniformity via Dummy Dielectric
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Solution Overview
Problem
Vertical field effect transistors (VFETs) face variations in gate length due to differences in gate metal height, primarily caused by the 'loading effect' from varying etch rates in gate trenches with different dimensions, leading to inconsistent device performance.
Innovation Solution
The method involves forming a hardmask on fins, selectively depositing a dummy dielectric on the hardmask, and then removing the dummy dielectric and hardmask to create uniform openings, ensuring uniform etching and recessing of the gate structure, thereby maintaining consistent gate length across all fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate metal height is used to control gate length in VFETs, then device footprint is decoupled from gate length, but gate length variations occur due to loading effect from varying etch rates
Solution Approach 1:
The patent applies preliminary action by forming a dummy dielectric layer on the gate structure before the main etching process. This dummy layer serves as a pre-prepared protective element that compensates for the loading effect during subsequent etching, ensuring uniform gate length across different trench dimensions while maintaining the advantage of gate length control independence from footprint.
Solution Approach 2:
The dummy dielectric layer acts as an intermediary element between the gate structure and the etching process. It mediates the loading effect by providing uniform protection during etching, allowing the gate metal height to control gate length without suffering from variations due to different trench dimensions.
2Manufacturing precision
If selective dummy dielectric deposition and removal is performed to create uniform openings, then gate length variations are minimized, but manufacturing process complexity increases
Solution Approach 1:
The patent applies homogeneity by creating uniform openings through selective dummy dielectric deposition and removal. The dummy dielectric layer is formed with uniform thickness across all gate structures, and its selective removal creates homogeneous opening dimensions, ensuring consistent gate length uniformity across different device regions despite the additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes or eliminates gate length variations by ensuring uniform recessing of the gate structure, resulting in consistent gate lengths across vertical transistors, which enhances device reliability and performance.
Implementation Method 1
selectively depositing a dummy dielectric on the hardmask
Implementation Method 2
selectively depositing a dummy dielectric on the hardmask
Implementation Method 3
selectively removing the dummy dielectrics and the hardmasks with respect to the dielectric layer and the gate structure
Data Source
AI summary
A semiconductor device includes a vertical transistor on a substrate. The vertical transistor includes at least one fin. A bottom source/drain is disposed on the substrate and around the at least one fin. A spacer layer is disposed on the bottom source/drain and around the at least one fin. A gate structure is disposed on the spacer layer and around the at least one fin. The gate length is the same or substantially the same on each side of the at least one fin.