Flowable Dielectric STI for Semiconductor Fin Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device fabrication processes involving Si and SiGe layers require a lower thermal budget to prevent intermixing and defect formation, leading to less robust shallow trench isolation (STI) oxide and increased STI oxide loss, which affects the efficiency and reliability of devices like nanowire and nanosheet FETs.
Innovation Solution
A method is developed to form a precursor semiconductor device structure by creating fin structures with sacrificial SiGe layers and Si channel layers, where the sacrificial layers are selectively etched and replaced with insulating flowable dielectric material, providing robust anchoring and isolation, thus maintaining a higher thermal budget without compromising device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a lower thermal budget is used to prevent intermixing of Si and SiGe layers, then layer integrity is improved, but STI oxide robustness deteriorates and STI oxide loss increases
Solution Approach 1:
The patent introduces an intermediary material layer between the Si/SiGe layer stack and the STI oxide. This intermediary layer acts as a protective buffer that prevents direct interaction between the low-thermal-budget processed semiconductor layers and the STI oxide, thereby maintaining both layer integrity and STI oxide robustness simultaneously. The intermediary layer absorbs thermal stress and prevents intermixing while preserving the STI oxide structure.
2Adaptability or versatility
If SiGe sacrificial layers are used in the layer stack, then device geometry flexibility is improved, but thermal budget requirements worsen due to intermixing risks
Solution Approach 1:
The intermediary material layer enables the use of SiGe sacrificial layers for creating complex device geometries (such as nanowire and nanosheet FETs) while protecting against thermal intermixing. This mediator allows the process to maintain the geometric flexibility benefits of SiGe layers without suffering from their thermal budget limitations.
Solution Approach 2:
The intermediary layer is formed in advance before subsequent high-temperature processing steps. This preliminary protective measure ensures that when thermal processing is later required for STI formation or other device steps, the SiGe layers are already protected from intermixing, enabling geometry flexibility without thermal budget constraints.
3Stability of the object's composition
If STI oxide is formed with reduced thermal budget, then layer intermixing is prevented, but STI oxide quality deteriorates
Solution Approach 1:
The intermediary material layer serves as a thermal buffer that decouples the thermal budget requirements of STI oxide formation from the Si/SiGe layer stack. This allows the STI oxide to be formed with sufficient thermal energy to achieve high quality and robustness, while the intermediary layer protects the underlying semiconductor layers from intermixing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more thermally stable fin structures with reduced leakage currents and improved device performance, enabling the fabrication of NW- or NSHFETs with enhanced process margins and robust STI oxide, facilitating the formation of semiconductor devices without the need for a reduced thermal budget.
Implementation Method 1
depositing an insulating material to fill the cavities, wherein the insulating material is formed of a flowable dielectric
Implementation Method 2
removing the sacrificial layers of each fin structure by a selective etching of the first semiconductor material
Data Source
Figure 1a~2b
Figure 3a~4b
Figure 5a~6b
AI summary
According to an aspect there is provided a method for forming a precursor semiconductor device structure, the method comprising: forming an initial layer stack comprising a sacrificial layer of a first semiconductor material and over the sacrificial layer a channel layer of a second semiconductor material; forming a set of fin structures by patterning trenches in the initial layer stack; forming at least one anchoring structure extending across the fin structures, and while the channel layers are anchored by the at least one anchoring structure: removing the sacrificial layers by a selective etching of the first semiconductor material, thereby forming a longitudinal cavity underneath the channel layer of each fin structure, and depositing an insulating material to fill the cavities, wherein the insulating material is formed of a flowable dielectric; and subsequently recessing the at least one anchoring structure and the insulating material to a level below the cavities such that the insulating material remains in the cavities to form insulating layers underneath the channel layers of each fin structure.