TFET Source Region Under Gate Dielectric for Drive Current
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Solution Overview
Problem
Conventional tunneling field-effect transistors (TFETs) suffer from low drive current due to the increased tunneling barrier width caused by spacer gaps between the SiGe source region and the gate stack, which negates the benefits of using SiGe in the source region.
Innovation Solution
The TFET structure is modified by positioning at least a portion of the source region underneath the gate dielectric, allowing the gate dielectric to overlap the source region, and using a SiGe source region with high Ge content and in-situ doped P+ SiGe to reduce the tunneling barrier width and increase drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an offset spacer is used between the SiGe source region and the gate stack, then the manufacturing process is simplified and alignment is easier, but the tunneling barrier width increases which reduces drive current
Solution Approach 1:
The patent removes the offset spacer that traditionally separates the SiGe source region from the gate stack. By extracting this spacer component, the source region can extend directly to the gate stack, minimizing the tunneling barrier width and maximizing drive current while maintaining manufacturability through alternative alignment control methods
2Productivity
If the source region is positioned closer to the gate stack, then the tunneling barrier width is reduced increasing drive current, but the risk of dopant fluctuation and manufacturing variability increases
Solution Approach 1:
The patent applies local quality by creating a graded SiGe source region where the germanium content varies spatially. The SiGe composition is optimized locally at different positions - higher Ge content near the tunneling region to minimize barrier width, and controlled Ge content further away to reduce dopant fluctuation effects, thus achieving both high drive current and improved reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the tunneling barrier width, enhancing the drive current capability of TFETs while maintaining the reliability of a silicon channel and minimizing dopant fluctuation issues.
Implementation Method 1
the gate induces sufficient band bending resulting in a reduction of the tunneling barrier width to less than 5 nanometers (nm). This leads to substantial band-to-band tunneling of electrons from the valence band of the P+ source region to the conduction band of the N+ drain region
Data Source
AI summary
A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).