Offset Drain GAAFET for High Voltage Operation
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Solution Overview
Problem
Existing semiconductor devices face challenges in operating at higher voltages without causing performance deterioration or component damage, particularly in gate-all-around field-effect transistor (GAAFET) devices, due to the formation of the source, gate, and drain in the same plane.
Innovation Solution
The semiconductor device structure incorporates a drain formed in a separate plane from the source and gate, allowing for increased drain area and reduced resistance, enabling operation at voltages between 1.2 volts to 3.3 volts without component deterioration, using a GAAFET technology with nanosheet channels and epitaxial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source, gate, and drain are formed in the same plane in conventional GAAFET devices, then the device structure is simple and fabrication is easier, but the device cannot operate at higher voltages without performance deterioration or component damage
Solution Approach 1:
The patent applies dimensionality change by moving the drain from the same plane as the source and gate to a separate plane, creating a three-dimensional offset drain structure. This spatial reconfiguration allows the drain to be positioned in a different layer or plane relative to the source-gate plane, enabling higher voltage operation without compromising the compactness of the device. The offset drain structure effectively adds a dimensional aspect to the device architecture, resolving the contradiction between reliability and structural simplicity.
2Reliability
If the drain area is increased to reduce resistance for high-voltage operation, then the on-resistance improves, but the device footprint increases
Solution Approach 1:
The offset drain structure utilizes a separate plane or layer to accommodate an enlarged drain area without expanding the device footprint in the primary plane. By positioning the drain in a different dimensional space (offset plane), the design achieves lower on-resistance through increased drain area while maintaining a compact footprint, as the extended drain region does not occupy additional space in the source-gate plane.
3Reliability
If conventional GAAFET structures are used, then fabrication processes are straightforward, but gate damage occurs at higher voltages
Solution Approach 1:
The offset drain structure positions the drain in a separate plane away from the gate, creating physical and electrical separation that prevents gate damage during high-voltage operation. This dimensional separation allows the drain to handle high voltages without directly exposing the gate to damaging electric fields or hot carriers, while the fabrication process remains compatible with existing GAAFET manufacturing techniques.
Data Source
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AI summary
A semiconductor device (100) such as, for example, a gate-all-around field-effect transistor (GAAFET) device suitable for operability under higher operating voltage conditions (e.g., 1.2 volts to 3.3 volts). The semiconductor device (100) includes a first channel (112) that is formed in a first plane (200) of the semiconductor device (100), a second channel (114) that is formed in a second plane (300) of the semiconductor device (100) different from the first plane (200), a drain (150) that is formed around the first channel (112), a gate (132) that is formed around the second channel (114), and a source (142) that is formed around the second channel (114).