Compressively Strained GAA Transistor Channel Layers
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Solution Overview
Problem
Current gate-all-around (GAA) transistor device processing results in defects due to discontinuous epitaxial source/drain growth fronts, leading to either no compressive or tensile strain in the channel, which affects the device's performance.
Innovation Solution
The method involves depositing source/drain structures within trenches through channel layers without inner spacers, allowing for continuous epitaxial growth and subsequent inner spacer deposition, thereby achieving compressive strain and minimizing crystallographic defects in the channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacers are deposited before source/drain epitaxial growth, then the source/drain structures are isolated during deposition, but discontinuous growth fronts merge resulting in crystallographic defects and no compressive strain in the channel
Solution Approach 1:
The invention removes the inner spacer structure entirely from the process flow. By eliminating the inner spacer that caused discontinuous growth fronts, the source/drain epitaxial material can grow continuously across the channel width without merging defects, while still achieving the desired compressive strain through the overall device geometry and material composition
Solution Approach 2:
The invention performs preliminary strain engineering through the source/drain material composition and device structure design before epitaxial growth occurs. By pre-configuring the trench dimensions, source/drain material composition (e.g., SiGe), and overall device geometry, the compressive strain is established in the channel before growth, avoiding the need for inner spacers that would disrupt growth continuity
2Ease of manufacture
If inner spacers are used during source/drain deposition, then deposition isolation is achieved, but the merged growth fronts result in tensile strain or no compressive strain in the channel
Solution Approach 1:
The invention extracts/removes the inner spacer component from the manufacturing process. By eliminating this isolation structure, the source/drain epitaxial growth proceeds as a continuous front across the entire trench, enabling the material composition and device geometry to generate the required compressive strain in the channel without interference from spacer-induced discontinuities
Solution Approach 2:
The invention changes the process parameters by removing the inner spacer deposition step and adjusting the source/drain material composition (e.g., using SiGe with appropriate germanium content). This parameter change allows the epitaxial growth to proceed continuously while the modified material properties and device geometry generate the necessary compressive strain in the silicon channel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances channel mobility and reduces defects, resulting in improved performance of pMOS transistors by ensuring a defect-free epitaxial source/drain structure with integrated compressive strain in the channel layers.
Implementation Method 1
positive epitaxial (p-EPI) source/drain deposition occurring from multiple discontinuous growth surfaces resulting in defects in the EPI when the growth fronts merge
Data Source
Figure 1
Figure 2~3
Figure 4A~4B
AI summary
An integrated circuit (IC) device (800B, 800C), and a method of forming the same. The IC device includes a transistor device comprising a multilayer stack that has a plurality of channel layers (Si channel) including a semiconductor material; a gate structure wrapped at least partially around the channel layers, the gate structure including a metal; an epitaxial source structure (112B) at a first lateral end of the multilayer stack; an epitaxial drain structure (112B) at a second lateral end of the multilayer stack opposite the first lateral end; and inner spacers (120B, 120C) between the gate structure and respective ones of the source structure and the drain structure, wherein the epitaxial source and drain structures are formed prior to removing the sacrificial semiconductor layers and forming the inner spacers, because of which the source and drain structures do not exhibit crystallographic defects extending from the inner spacers. The source drain structures furthermore exert compressive strain on the channel layers.