Asymmetric Gate Overhang for CMOS Dual Stress Liner Optimization
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Solution Overview
Problem
CMOS transistors in deep submicron regimes face performance limitations due to reduced scaling and design constraints, particularly with dual stress liner technology where stress orientation affects mobility and performance of NMOS and PMOS transistors, and existing design rules restrict optimal placement of the DSL boundary.
Innovation Solution
Increasing the gate overhang of active for NMOS transistors beyond minimum design rules while maintaining PMOS transistors at minimum design rules to optimize the position of the dual stress liner boundary, thereby enhancing electron and hole mobility, and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate overhang of active for NMOS transistors is increased beyond minimum design rules, then electron mobility is improved, but chip area increases and design rule constraints are violated
Solution Approach 1:
The patent applies asymmetric gate overhang design where NMOS transistors have extended gate overhang beyond minimum design rules while PMOS transistors maintain minimum gate overhang. This asymmetric configuration optimizes electron mobility in NMOS devices without proportionally increasing overall chip area, as the asymmetry is localized to specific transistor types rather than applied uniformly across all devices.
Solution Approach 2:
The patent implements local quality by selectively extending gate overhang only for NMOS transistors that require enhanced electron mobility, while keeping PMOS transistor gate overhang at minimum design rules. This localized modification allows performance optimization in specific areas without unnecessarily increasing the entire chip area.
2Reliability
If the DSL boundary is moved to optimize transistor performance, then mobility is improved, but design rule constraints and layout flexibility are reduced
Solution Approach 1:
The patent applies preliminary action by pre-positioning the DSL boundary at an optimized location that maximizes hole mobility in PMOS transistors. This predetermined boundary placement is incorporated into the design rules and layout methodology, allowing subsequent transistor placements to automatically benefit from the optimized stress region positioning without requiring real-time optimization decisions.
3Reliability
If design rules are relaxed to allow greater gate overhang, then transistor performance is improved, but manufacturing precision and design control are reduced
Solution Approach 1:
The patent applies parameter changes by modifying the gate overhang parameter specifically for NMOS transistors beyond the minimum design rule value. This controlled parameter change allows performance optimization while maintaining manufacturing precision through systematic updates to design rule sets, ensuring that the extended overhang dimensions are precisely controlled and manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases NMOS transistor electron mobility by approximately 1.75% and PMOS transistor hole mobility, leading to improved drive current and overall performance in integrated circuits.
Implementation Method 1
Compressive stress when applied parallel to the current flow increases hole mobility for PMOS transistors thus improving PMOS transistor performance. Tensile stress when applied parallel to the current flow increases electron mobility in NMOS transistors improving performance.
Data Source
AI summary
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.