Transistor TRIZ Cases

Sidewall spacers generate distinct LOCOS field relief oxide thicknesses to support multiple drain voltages without increasing process complexity.

A semiconductor integrated circuit uses a well-in-well protection element to reduce parasitic capacitance.

A trench field effect transistor uses a laterally extended gate dielectric to reduce electrical field concentration at device corners.

Segmented integrated circuit devices use bonded semiconductor substrates to resolve manufacturing cost versus signal fidelity trade-offs in RF switches.

A plasma nitridation and oxidation process creates a uniform interface layer on high aspect ratio bottom electrodes.

Overlapping transparent electrodes with an oxide semiconductor layer increase capacitance, maintaining high aperture ratios in display devices.

A FinFET uses a cloak-shaped active region and wrapping gate to control the channel.

Zigzag edge MoS2 nano-ribbons create ohmic contacts that resolve doping difficulties while boosting the ON/OFF ratio.

A semiconductor manufacturing method uses photoresist patterning and liftoff to deposit high-dielectric constant films on MIM capacitor electrodes.

A contact plug extends through the semiconductor substrate isolation region to connect with a transistor block layer.

Self-aligned spacers define buried contacts, reducing photolithography steps and misalignment in DRAM fabrication.

Segmented zirconium oxide and carbo-oxynitride layers suppress leakage current while maintaining uniform threshold voltage during annealing.

Extends NMOS gate overhang beyond minimum design rules to optimize dual stress liner positioning.

Shared P-type doped wells modulate nMOS and pMOS threshold voltages using back-gate biasing, reducing manufacturing complexity and leakage.

A semiconductor nonvolatile memory element regulates output voltage through threshold voltage adjustment using external electrical signals.

Segmenting amorphous silicon for zone-specific laser energy compensates for thickness variations, ensuring uniform grain distribution.

Segmented scan chain registers retain display parameters while power stops, reducing consumption without losing data across flexible regions.

Extending active areas and gate lines in a dummy cell array maintain uniform process conditions across the wafer, reducing layout design time.

Biased dummy areas flank standard cell active regions to reduce local layout effects from peripheral structures.

A vertical high-voltage MOS transistor reduces trench pitch through segmented field plates and LDD regions.

Dummy electrodes and insulating films preserve resistance uniformity in a compact D/A converter layout.

Variable lateral widths in FinFET source/drain regions resolve the trade-off between operating speed and electrical failure rates.

Wet etching removes sacrificial layers, preventing dry etch damage to the SiGe stress layer and maintaining channel compression.

A VDMOS and JFET integrated semiconductor device uses shared electrodes to enable self-driven operation without secondary voltage.

Conformal spacer deposition over dummy gates enables simultaneous removal and recess formation, reducing cycle time while maintaining precision.

Laser annealing transitions piezoelectric films at 300 to 400 degrees Celsius, enabling flexible substrates without high-temperature damage.

A semiconductor memory cell configuration cancels transistor threshold voltages during data write operations to retain accurate voltage levels.

Pre-formed protrusions guide photomask exposure to prevent misalignment etching and moisture penetration in display devices.

An oxide layer on the gate electrode protects the semiconductor in an array substrate.

A fingerprint photocurrent detection unit converts acquired photocurrent into a square wave signal using a dedicated conversion circuit.

Homogeneous gate spacers eliminate lattice mismatch defects between active patterns and spacers, improving carrier mobility in multi-gate transistors.

Selective removal of intermediate patterned layers before etching prevents over-etching damage and ensures uniform fin spacing in high-density circuits.

Silicide backside contact features connect power rails to source drain features, reducing routing resistance in advanced integrated circuits.

Dummy gates cover active fin ends and contact via spacers to reduce short channel effects while maintaining manufacturing precision.

Plasma cleaning removes surface oxides from phase change material layers, enabling void-free gap filling without high-temperature device damage.

Integrating driver circuits on the same substrate as pixels reduces manufacturing costs while maintaining high field effect mobility.

Silicon oxide and silicon nitride passivation layers prevent oxide semiconductor deterioration while maintaining high ON/OFF ratios in thin film transistors.

Composite wiring structures with copper core and diffusion barrier films reduce signal delay caused by high resistance in large display areas.

Segmenting the gate electrode into isolated sub-gates applies independent voltages to suppress leakage currents and enhance subthreshold characteristics.

U-shaped resistive liners between semiconductor fins enable precise resistance adjustment through dimensional control.

A semiconductor device structures a bipolar transistor mesa taller than a field effect transistor gate region to enhance high-frequency performance.

Wrap-around contacts expand source/drain interface area to reduce resistance while maintaining vertical integration and electrical isolation.

Interconnect layers separate electrodes from the semiconductor channel, reducing ion bombardment damage during dry etching.

A silicon carbide semiconductor device with an inclined interface region enhances carrier mobility through specific crystallographic orientation.

A drive circuit uses set and reset pulse signals to control semiconductor device states.

A step-shaped gate structure crosses over multiple fin structures to increase channel width and read current in FinFET static random access memory.

Parallel n-type and p-type back end transistors form an access transmission gate that mitigates source degeneration in resistive random access memory cells.

A bypass unit with a transistor diverts current away from the body diode during dead time to reduce voltage stress.

Optimized light blocking layer shading portions and specific color filter transmittance improve the aperture ratio of oxide semiconductor TFT displays.