Back-Surface Contact Plug in Semiconductor Substrate

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving higher integration and flexibility in design due to potential short circuits between contact electrodes and gate electrodes, particularly in bulk semiconductor structures, where processing and alignment accuracy variations are concerns.

Innovation Solution

A semiconductor device configuration with a contact plug extending from the front surface to the back surface in the isolation region of the semiconductor substrate, avoiding the transistor region, and a block layer or metal layer connecting the contact plug to the transistor, ensuring electrical isolation and flexibility in design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the contact electrode is disposed on the back surface of the substrate to achieve flexibility in wiring path, then design flexibility is improved, but short circuit risk between contact electrode and gate electrode increases due to processing variation and alignment accuracy issues

Engineering Contradiction:

Improvedesign flexibilityVSAvoidshort circuit risk

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

An insulating layer is introduced as an intermediary between the contact electrode and the gate electrode. This insulating layer is disposed between the contact electrode extending through the substrate and the gate electrode, preventing direct contact and potential short circuits while maintaining the back-surface contact configuration for design flexibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The contact electrode is segmented into multiple portions: a first contact portion extending from the back surface through the substrate, and a second contact portion disposed above the insulating layer. This segmentation allows the contact electrode to be electrically isolated from the gate electrode while maintaining connectivity functionality.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If the contact electrode passes through the substrate to connect to the silicide layer, then wiring path flexibility is improved, but alignment accuracy requirements increase leading to potential short circuits

Engineering Contradiction:

Improvewiring path flexibilityVSAvoidalignment accuracy

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The insulating layer serves as a mediator that reduces alignment precision requirements. By providing a broad insulating region between the contact electrode and gate electrode, the system tolerates greater variation in contact electrode positioning without risking short circuits.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If higher integration is achieved with increased transistor density, then integration density is improved, but the risk of short circuit between contact and gate electrodes increases due to closer spacing

Engineering Contradiction:

Improveintegration densityVSAvoidshort circuit risk

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The insulating layer extends in the vertical dimension between the contact electrode and gate electrode, providing electrical isolation that is independent of the horizontal spacing between components. This allows higher integration density in the planar direction while maintaining reliability through vertical insulation.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10879299B2Semiconductor device with transistor in semiconductor substrate and insulated contact plug extending through the substrate

Publication Date: 2020.12.29 SONY GROUP CORP

AI summary

A semiconductor device including a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.