RF Switch With Segmented SOI Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional RF switches for wireless communication devices face challenges in achieving high signal fidelity, low insertion loss, and minimal signal distortion while being cost-effective, particularly due to difficulties in implementing circuit elements on thin silicon films and high manufacturing costs associated with gallium arsenide semiconductor transistors.
Innovation Solution
The integrated circuit device employs a configuration with separate sets of semiconductor substrates and transistors, including metal-oxide-semiconductor field-effect transistors and laterally diffused metal oxide semiconductor field-effect transistors, connected through dielectric layers and interconnect members, optimized through wafer bonding and interconnection techniques, to form a RF switch and amplifier circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thin film silicon-on-insulator (SOI) MOSFET is used for the RF switch, then manufacturing cost is reduced compared to gallium arsenide, but the silicon thin film thickness (0.1 to 0.6 microns) makes it substantially difficult to implement circuit elements such as switch control circuit logic and amplifier elements
Solution Approach 1:
The patent divides the device into two separate substrates: a first substrate containing the RF switch and a second substrate containing the circuit elements (logic control and amplifier). This segmentation allows each substrate to be optimized independently - the first substrate uses thin film SOI MOSFET for cost-effective RF switching, while the second substrate provides sufficient thickness and material properties for implementing complex circuit elements, thereby resolving the contradiction between manufacturing cost and circuit implementation capability
Solution Approach 2:
The patent introduces an intermediary bonding interface between the two substrates to electrically connect the RF switch on the first substrate with the circuit elements on the second substrate. This intermediary connection allows the thin film SOI MOSFET to function as an RF switch while being controlled by and driving amplifier elements implemented on a separate substrate with appropriate film thickness, thus enabling both cost-effectiveness and full circuit functionality
2Reliability
If gallium arsenide semiconductor transistors are used for the RF switch, then signal fidelity and performance are improved, but processing, manufacturing and packaging costs are substantially high
Solution Approach 1:
The patent replaces expensive gallium arsenide semiconductor transistors with cheaper silicon-based thin film SOI MOSFETs for the RF switch function. While silicon has different material properties, the thin film SOI structure is engineered to achieve acceptable RF performance at significantly lower manufacturing cost, aligning with the principle of using cost-effective materials when performance requirements can be met through structural optimization rather than expensive material selection
3Device complexity
If multiple circuit elements are integrated on a single thin silicon film substrate, then device complexity is reduced, but the thin film thickness (0.1 to 0.6 microns) substantially prevents successful implementation of these elements
Solution Approach 1:
The patent transitions from a two-dimensional integration approach (all elements on one thin film) to a three-dimensional stacked architecture with two separate substrates bonded together. This dimensional change allows circuit elements to be implemented on the second substrate where sufficient material thickness and appropriate substrate properties exist, while the first substrate maintains its thin film structure optimized for RF switching, thereby achieving both integration and manufacturing precision
Data Source
AI summary
An integrated circuit device may include the following elements: a first semiconductor substrate; a first transistor set positioned in the first semiconductor substrate; a first dielectric layer covering a gate electrode of the first transistor set; a first interconnect member positioned in the first dielectric layer and electrically connected to the first transistor set; a second semiconductor substrate; a second transistor set positioned in the second semiconductor substrate and structurally different from the first transistor set; a second dielectric layer connected to the first dielectric layer, positioned between the first dielectric layer and the second semiconductor substrate, and covering a gate electrode of the second transistor set; and a second interconnect member positioned in the second dielectric layer, electrically connected to a terminal of the second transistor set, and electrically connected to the first interconnect member.