RRAM Access Transmission Gate for Source Degeneration

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Solution Overview

Problem

Resistive random access memory (RRAM) cells face limitations due to low drive strength and source degeneration issues, exacerbated by wafer-to-wafer and die-to-die variability, which restrict switching currents and reliability, especially with conventional transistors that require higher voltages for operation.

Innovation Solution

The implementation of an access transmission gate comprising an n-type back end transistor in parallel with a p-type back end transistor, allowing for high current flow in both directions and reducing source degeneration, thereby enhancing the switching capabilities and reliability of RRAM cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional transistors with high Vt are used to ensure reliability at high bias, then reliability is improved, but drive strength deteriorates

Engineering Contradiction:
ImprovereliabilityVSAvoiddrive strength
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent combines an NMOS transistor and a PMOS transistor in parallel to form a transmission gate. This merging of complementary transistor types allows the structure to leverage the strengths of both device types, achieving high current drive capability while maintaining reliability through the complementary nature of the transistors.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The transmission gate structure serves multiple functions: it provides bidirectional current flow capability, acts as a switch with high on-state current, and eliminates source degeneration effects. This multi-functionality allows a single structure to address multiple performance requirements simultaneously.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If conventional transistors are used in RRAM cells, then device simplicity is maintained, but source degeneration issues worsen

Engineering Contradiction:
Improvedevice simplicityVSAvoidsource degeneration
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

By merging NMOS and PMOS transistors in parallel, the transmission gate structure inherently compensates for source degeneration effects that plague conventional single-transistor designs. The complementary transistors balance each other's degradation, improving reliability without significantly increasing device complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If conventional transistors require higher voltages for operation, then switching reliability is improved, but voltage requirements worsen

Engineering Contradiction:
Improveswitching reliabilityVSAvoidvoltage requirements
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The transmission gate structure changes the voltage-parameter characteristics by providing high current drive capability at lower voltage thresholds. The parallel configuration of complementary transistors allows the structure to achieve reliable switching at reduced voltage levels compared to conventional high-Vt transistors.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10811461B2Access transmission gate
Publication Date: 2020.10.20 INTEL CORP
  • US10811461B2 patent drawing
  • US10811461B2 patent drawing
  • US10811461B2 patent drawing

AI summary

Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.