Semiconductor Integrated Circuit ESD Protection with Floating Node

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Solution Overview

Problem

Existing semiconductor integrated circuits face challenges with signal wave distortion due to high parasitic capacitance in ESD protection elements, particularly when dealing with fluctuating signal DC levels, and thyristors have high trigger voltage issues, which can damage internal circuits.

Innovation Solution

A semiconductor integrated circuit with a protection element formed by two diodes connected in a back-to-back configuration on the same substrate, utilizing a well-in-well structure with a floating node, which reduces parasitic capacitance and allows for bidirectional surge current passage without distorting signals across varying voltage ranges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a GGMOS protection element is used, then ESD protection is provided, but large parasitic capacitance causes signal attenuation and distortion

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidsignal attenuation and distortion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The protection element is segmented into two separate diodes connected in series between the signal line and power supply lines, rather than using a single GGMOS transistor. This segmentation reduces the parasitic capacitance affecting the signal path while maintaining ESD protection functionality through the series diode configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate terminal of the protection element is extracted and left floating (not connected to any potential), removing the capacitive coupling effect that would otherwise exist between the gate and source/drain terminals. This extraction eliminates the large parasitic capacitance problem inherent in GGMOS structures.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If a unidirectional diode protection element is used, then ESD protection is provided, but signal clipping occurs when signal potential exceeds VDD or falls below VSS

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidsignal waveform distortion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The protection element uses asymmetric diode orientation where the cathodes face the signal line and anodes are connected to power supply lines. This asymmetric configuration allows the diodes to remain reverse-biased during normal signal operation, preventing signal clipping, while still providing protection when voltage excursions occur.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The protection element dynamically responds to voltage conditions: during normal operation the diodes remain off (high impedance state), preserving signal integrity; during ESD events or voltage excursions, the diodes turn on (low impedance state) to provide protection. This dynamic behavior eliminates the static signal clipping problem of conventional diode protectors.

Inventive Principle:
Principle #15Dynamics

3Reliability

If a thyristor is used as ESD protection element, then low ON resistance provides good current handling, but high trigger voltage may damage internal circuit before thyristor turns ON

Engineering Contradiction:
Improvecurrent handling capabilityVSAvoidtrigger voltage control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The protection element uses diodes with adjustable breakdown characteristics instead of a fixed-threshold thyristor. By selecting diodes with appropriate reverse breakdown voltages, the protection threshold can be precisely controlled to match the internal circuit's withstand voltage, preventing premature damage while maintaining low ON resistance when activated.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively suppresses signal wave distortion and eliminates surges with low capacitance, ensuring the internal circuit remains undistorted across a wide voltage range without the need for additional power source protection circuits.

Implementation Method 1

A semiconductor integrated circuit having a protection element with a small parasitic capacitance for preventing or suppressing signal wave distortion

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS8093623B2Semiconductor integrated circuit
Publication Date: 2012.01.10 SONY GROUP CORP
  • US8093623B2 patent drawing
  • US8093623B2 patent drawing
  • US8093623B2 patent drawing

AI summary

Disclosed herein is a semiconductor integrated circuit including a protected circuit; and a protection element formed on the same semiconductor substrate as the protected circuit and adapted to protect the protected circuit, wherein the protection element includes two diodes having their anodes connected together to form a floating node and two cathodes connected to the protected circuit, the two diodes are formed in a well-in-well structure on the semiconductor substrate, and the well-in-well structure includes a P-type well forming the floating gate, an N-type well which surrounds the surfaces of the P-type well other than that on the front side of the substrate with the deep portion side of the substrate so as to form the cathode of one of the diodes, and a first N-type region formed in the P-type well so as to form the cathode of the other diode.