FinFET SRAM Layout with Step-Shaped Gate for Read Speed
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Solution Overview
Problem
Current SRAM architectures face challenges in producing desirable patterns as the pitch of the exposure process decreases, leading to difficulties in enhancing exposure quality and improving yield and read speed.
Innovation Solution
The proposed SRAM layout features fin field-effect transistors (FinFETs) with step-shaped gate structures that cross over multiple fin structures, increasing channel width and read current, thereby improving read speed and exposure quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of the exposure process is decreased to increase integration density, then more devices can be packed into a smaller area, but the ability to produce desirable patterns deteriorates
Solution Approach 1:
The gate structure is segmented into multiple parts (first gate part, second gate part, third gate part) that can be independently formed and positioned. This segmentation allows each gate portion to be precisely controlled during the exposure process, maintaining pattern quality even at reduced pitch sizes by treating different gate sections as separate formable units
Solution Approach 2:
The invention transitions from a conventional planar gate structure to a three-dimensional stacked gate configuration. By arranging gate parts in vertical layers (different dimensions) rather than only horizontal spacing, the design achieves higher device density without proportionally reducing the lateral pitch, thereby maintaining exposure pattern quality while increasing integration density
2Speed
If the channel width is increased to improve read current and read speed, then the read performance is improved, but the area occupied by each device increases
Solution Approach 1:
The gate structure extends in the vertical dimension with multiple stacked gate parts, effectively increasing the channel width without expanding the lateral footprint. This vertical stacking allows the channel to accommodate more fin structures (first fin, second fin, third fin) beneath the extended gate, thereby increasing read current and read speed while maintaining compact device area
Solution Approach 2:
Multiple fin structures are nested beneath the stacked gate parts, with each gate part controlling a corresponding fin structure. This nesting arrangement allows the channel width to be effectively increased by stacking control elements vertically, enabling higher read performance within a confined lateral space
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances read speed and exposure quality by increasing the channel width of pull-down devices, allowing the SRAM to maintain high yield and fast read speeds even at reduced pitch sizes.
Implementation Method 1
each of the at least one pull-up device (PLs), the at least one pull-down devices (PDs), and the at least two pass gate devices (PGs) includes a fin field-effect transistor (FinFET)
Data Source
AI summary
A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.