Lateral Gate Dielectric Extension for High Voltage Breakdown
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Solution Overview
Problem
High voltage field effect transistors face surface breakdown voltage issues due to complex extended low doped drain structures, which increase process complexity and cost.
Innovation Solution
A field effect transistor design featuring a trench with a continuous dielectric material layer that fills the entire volume, a gate electrode overlying the center portion of the dielectric, and source and drain extension regions formed under the peripheral portions of the gate dielectric, reducing electrical field concentration at the bottom corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex extended low doped drain structures or shallow trench isolation are used to improve surface breakdown characteristics, then breakdown voltage performance is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the complex extended low doped drain structure and shallow trench isolation from the device architecture. Instead, it uses a simple planar gate dielectric structure that laterally extends beyond the gate electrode edges, achieving surface breakdown improvement without the complexity of previous structures
Solution Approach 2:
The patent inverts the conventional approach by extending the gate dielectric laterally beyond the gate electrode edges rather than using complex drain structures. This reverse thinking creates a new mechanism for improving surface breakdown characteristics that avoids the complexity of traditional solutions
2Reliability
If complex extended low doped drain structures or shallow trench isolation are used to improve surface breakdown characteristics, then breakdown voltage performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive complex extended low doped drain structure and shallow trench isolation processes from the manufacturing flow. The simplified gate dielectric extension structure requires standard fabrication processes, significantly reducing manufacturing cost while maintaining reliability
Solution Approach 2:
The patent uses a simple gate dielectric material that can be deposited using standard, cost-effective processes rather than requiring expensive specialized structures. The dielectric extension is formed as a straightforward planar layer that is economical to manufacture
3Area of moving object
If device size is reduced for scaling, then integration density is improved, but breakdown voltage performance may deteriorate
Solution Approach 1:
The patent addresses the scaling challenge by extending the gate dielectric in the lateral dimension beyond the gate electrode edges. This dimensional extension compensates for the reduced device size, maintaining adequate breakdown voltage performance even as the overall device footprint is reduced for higher integration density
Data Source
AI summary
A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes a gate dielectric that fills an entire volume of the trench. A gate electrode is formed over the gate dielectric such that the gate electrode overlies a center portion of the gate dielectric and does not overlie a first peripheral portion and a second peripheral portion of the gate dielectric that are located on opposing sides of the center portion of the gate dielectric. After formation of a dielectric gate spacer, a source extension region and a drain extension region are formed within the semiconductor substrate by doping respective portions of the semiconductor substrate.