FinFET Source/Drain Regions with Variable Lateral Widths
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Solution Overview
Problem
The rapid downsizing of semiconductor devices has led to increased electrical failures during manufacturing, necessitating a solution to ensure reliable operating characteristics and prevent short circuits.
Innovation Solution
A semiconductor device design featuring fin active region patterns with source/drain regions, where the source/drain regions have specific lateral width configurations and are doped with different conductivity types, integrated with a device isolation layer and spacer patterns to enhance structural integrity and reduce electrical failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the design rule of semiconductor devices is sharply reduced to achieve higher operating speeds, then the operating speed increases, but electrical failures increase during manufacturing processes
Solution Approach 1:
The source/drain regions are formed with different lateral widths at different locations: a first lateral width at the lower portion and a second lateral width at the upper portion. This local variation in dimensions allows optimization of electrical characteristics in different regions while maintaining manufacturing reliability, directly addressing the contradiction between speed and reliability.
Solution Approach 2:
The invention introduces a vertical dimension to the source/drain region geometry by creating varying lateral widths at different heights. This three-dimensional structure (with different widths at lower and upper portions) provides additional degrees of freedom for optimizing device performance without further reducing the planar design rule, thus improving speed without compromising reliability.
2Productivity
If the lateral width of source/drain regions is reduced to achieve further downsizing, then device density increases, but structural integrity and volume of source/drain regions deteriorate
Solution Approach 1:
The source/drain region is segmented into a lower portion and an upper portion, each with different lateral widths. The lower portion has a larger lateral width to provide structural integrity and sufficient volume, while the upper portion has a smaller lateral width to increase device density. This segmentation resolves the contradiction between density and structural integrity.
Solution Approach 2:
Different lateral widths are applied to different portions of the source/drain region: the lower portion maintains a larger width for structural support, while the upper portion uses a smaller width for density optimization. This localized differentiation allows simultaneous achievement of high density and structural integrity.
3Ease of manufacture
If uniform lateral width is used for source/drain regions to simplify manufacturing, then manufacturing complexity decreases, but electrical characteristics and reliability deteriorate
Solution Approach 1:
The device isolation layer is formed with a specific pattern before source/drain region formation, which preliminarily defines the lateral width variation of the source/drain regions. This preliminary structuring simplifies subsequent manufacturing steps while ensuring the source/drain regions achieve the desired non-uniform geometry for optimal electrical characteristics.
Solution Approach 2:
The device isolation layer acts as an intermediary structure that enables the formation of source/drain regions with varying lateral widths. By using the device isolation layer as a template or guide, the manufacturing process achieves complex geometry without proportionally increasing process complexity, maintaining ease of manufacture while improving electrical characteristics.
Data Source
AI summary
A semiconductor device includes a substrate having a fin active region pattern having a protruding shape, a device isolation layer pattern covering a side surface of a lower portion of the fin active region pattern, a spacer pattern covering a side surface of a portion of the fin active region pattern that protrudes from a top surface of the device isolation layer pattern, and a source/drain region in contact with a top surface of the fin active region pattern and a top surface of the spacer pattern.