FDSOI Transistor Threshold Voltage Control via Shared Well Doping
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Solution Overview
Problem
Current integrated circuits with FDSOI transistors require complex manufacturing methods to achieve a variety of threshold voltages, leading to increased leakage and complexity, especially when trying to minimize SiGe channel leakages while modulating pMOS transistor threshold voltages.
Innovation Solution
The integrated circuit design includes nMOS and pMOS transistors with multiple threshold voltage levels using UTBOX FDSOI technology, simplifying the structure by using shared P-type doped wells and biasing terminals to reduce the number of gate materials and manufacturing complexity, while achieving a range of threshold voltages through channel doping and stress configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex manufacturing methods are used to achieve various threshold voltages in FDSOI transistors, then the threshold voltage control is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the functions of multiple separately doped wells into a single shared P-type doped well structure. Instead of using separate N-doped and P-doped wells for different transistor types, the invention uses one shared P-type well that serves both nMOS and pMOS transistors, thereby reducing manufacturing complexity while maintaining precise threshold voltage control through selective doping regions within the shared well.
Solution Approach 2:
The shared P-type doped well structure performs multiple functions simultaneously: it serves as the substrate for both nMOS and pMOS transistors, provides threshold voltage modulation through back-gate biasing, and enables precise control of carrier concentrations in different channel regions. This multi-functional design reduces the number of manufacturing steps and structural elements required.
2Adaptability or versatility
If SiGe channels are used to modulate pMOS transistor threshold voltages, then the threshold voltage modulation capability is improved, but leakage increases
Solution Approach 1:
The patent applies local quality by creating distinct doping regions within the shared P-type well: lightly doped regions beneath nMOS channels to reduce leakage, and heavily doped regions beneath pMOS channels to enable threshold voltage modulation. This spatial variation in doping concentration allows each transistor type to have optimized local properties - low leakage for nMOS and high modulation capability for pMOS - without the harmful effects affecting both types uniformly.
3Adaptability or versatility
If multiple gate materials with various work functions are used, then the threshold voltage range is expanded, but the manufacturing process complexity increases
Solution Approach 1:
The patent achieves a wide threshold voltage range by changing the electrical parameters (doping concentrations) within a single gate material system rather than using multiple gate materials with different work functions. By varying the P-type doping concentrations in different regions of the shared well and applying different back-gate bias voltages, the invention accomplishes precise threshold voltage control across a wide range while maintaining a simplified single-material gate manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a large variety of threshold voltages with a reduced number of gate materials, simplifying the manufacturing process and minimizing leakage, thereby enhancing the efficiency and reliability of the integrated circuit.
Implementation Method 1
The threshold voltage of the various transistors is in particular adjusted by various biases of P-doped wells and of back gates formed underneath an ultra-thin insulation layer
Implementation Method 2
P-doped wells and of back gates formed underneath an ultra-thin insulation layer
Implementation Method 3
back gates formed underneath an ultra-thin insulation layer... various biases of P-doped wells and of back gates
Implementation Method 4
Such a diode increases the time to establish the biasing of the back gates
Data Source
AI summary
An integrated circuit comprising: first to third nMOS transistors with different threshold voltages, and first to third pMOS transistors with different threshold voltages, the nMOS transistors having channel regions made of silicon subjected to tensile stress and/or said pMOS transistors having channel regions made of SiGe subjected to compressive stress; a first well and a second well that are arranged underneath the nMOS transistors and underneath the pMOS transistors, respectively, with one and the same doping; two nMOS gate stacks comprising one and the same material, two of the nMOS gate stacks comprising materials having separate work functions, an nMOS gate stack having one and the same material as a pMOS gate stack, with the equation: Gp*Vdds−Gn*Gnds=Sn*|σn|+Sp*(|σp|−1.65*109)−VarCais+K.