Bipolar Transistor Mesa Height Optimization

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Solution Overview

Problem

Existing semiconductor devices with bipolar transistors have suboptimal high-frequency characteristics and complex manufacturing processes, particularly in HBTs with mesas surrounded by isolation regions.

Innovation Solution

Incorporating a field effect transistor with a source, drain, and gate region, where the mesa height is greater than the gate region, utilizing damascene-type techniques and sacrificial emitter regions to improve bipolar transistor speed and simplify manufacturing, while minimizing thermal stress and parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the mesa height is increased to improve high-frequency characteristics, then the bipolar transistor speed improves, but the manufacturing complexity increases due to additional CMP process steps

Engineering Contradiction:
Improvebipolar transistor speedVSAvoidmanufacturing process complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The field effect transistor is manufactured in advance before the bipolar transistor, allowing the mesa to be formed to a height greater than the gate region before FET processing. This preliminary action enables subsequent CMP steps to planarize the surface without damaging the FET, as the FET is already in place and can be protected during the planarization process.

Inventive Principle:
Principle #10Preliminary action

2Speed

If damascene-type techniques are used to improve bipolar transistor speed, then the high-frequency characteristics improve, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvebipolar transistor speedVSAvoidmanufacturing ease
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The patent combines the manufacturing of bipolar and field effect transistors into a single integrated process flow. By manufacturing the FET first and then forming the bipolar transistor mesa on the same substrate, the patent merges two separate manufacturing sequences into one unified process, reducing overall complexity despite using advanced techniques like damascene methods.

Inventive Principle:
Principle #5Merging (Combining)

3Object-affected harmful factors

If the field effect transistor is manufactured earlier to allow mesa height greater than gate region, then thermal stress on bipolar transistor is reduced, but the process sequence becomes more complex

Engineering Contradiction:
Improvethermal stress on bipolar transistorVSAvoidprocess sequence complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The field effect transistor is manufactured in advance before the bipolar transistor mesa is formed. This preliminary manufacturing of the FET allows the subsequent formation of a taller mesa structure without exposing the bipolar transistor to excessive thermal stress during FET processing, as the FET processing occurs before the high-temperature bipolar steps.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances high-frequency performance and simplifies the manufacturing process by allowing uniform deposition of insulating layers and reducing thermal stress on existing transistors, resulting in faster and more efficient bipolar transistors with improved high-frequency characteristics.

Implementation Method 1

The use of said damascene-type techniques implies the use of one or more CMP (=Chemical Mechanical Polishing) process steps

Methodology Applied
Scientific EffectChemical Mechanical Polishing:

Implementation Method 2

it is very well possible to deposit an insulating layer, such as a silicon dioxide layer, uniformly over the mesa, for example by means of CVD (=Chemical Vapor Deposition)

Methodology Applied
Scientific EffectChemical Vapor Deposition: Chemical Vapour Deposition

Data Source

PatentUS8373236B2Semiconductor device and method of manufacturing such a device
Publication Date: 2013.02.12 NXP BV
  • US8373236B2 patent drawing
  • US8373236B2 patent drawing
  • US8373236B2 patent drawing

AI summary

The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.