Semiconductor Memory Cell With Threshold Voltage Cancellation
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing memory capacity while maintaining data reliability due to variations in transistor electrical characteristics, which affect the retention of multiple voltage levels in memory cells, leading to decreased data accuracy and increased circuit area.
Innovation Solution
A semiconductor device with a memory cell configuration that includes multiple transistors and capacitors, where data voltages are written and read by canceling threshold voltages, allowing for accurate data conversion and reduced circuit area through the use of silicon and oxide semiconductor layers in different configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of data voltages is increased to improve memory capacity, then memory capacity is improved, but data reliability deteriorates due to voltage level variation from transistor electrical characteristic variation
Solution Approach 1:
The invention changes the parameter of voltage level representation by using differential voltages (Vdh and Vdl) instead of absolute voltage levels. This allows the memory to maintain multiple data states while being insensitive to transistor threshold voltage variations, thus preserving data reliability while increasing memory capacity.
Solution Approach 2:
The invention introduces reference voltages (VrefH and VrefL) as intermediary elements that mediate between the stored differential voltages and the readout circuitry. These reference voltages serve as stable comparison points that enable accurate data determination despite variations in transistor characteristics.
2Quantity of substance
If more voltage levels are retained in the memory cell, then memory capacity is improved, but measurement precision deteriorates because data becomes hard to determine when voltage levels vary
Solution Approach 1:
The invention transforms the measurement approach by using differential voltage measurement (comparing Vdh and Vdl) rather than absolute voltage level measurement. This differential approach maintains precision even when the number of voltage levels increases, because the measurement depends on the voltage difference rather than the absolute levels.
Solution Approach 2:
The invention establishes equipotential reference levels (VrefH and VrefL) that provide stable comparison points for determining stored data. By comparing the differential voltages against these reference levels, the system achieves precise data determination regardless of the number of voltage levels used to encode data.
3Quantity of substance
If traditional memory cell structures are used to retain multiple voltage levels, then memory capacity can be increased, but device complexity increases and circuit area expands
Solution Approach 1:
The invention makes the memory cell structure universal by using the same basic configuration (transistors and capacitors) for both data storage and data readout operations. The same transistors that store data are also used to control the readout process, eliminating the need for separate dedicated readout circuitry and reducing overall device complexity.
Solution Approach 2:
The invention merges the data storage function and data access function into a unified memory cell structure. The capacitors store data voltages while the transistors simultaneously serve as both storage control elements and readout switches, combining multiple functions into fewer components and reducing circuit area.
Data Source
AI summary
To provide a semiconductor device having large memory capacity and high reliability of data or a small-size semiconductor device having a small circuit area. A memory cell includes first and second data retention portions capable of storing multilevel data. A data voltage is written to the first data retention portion from a first wiring through a transistor and a second wiring, and a data voltage is written to the second data retention portion from the second wiring through a transistor and the first wiring. With the configuration, data voltages reduced by the threshold voltages of the transistors can be retained in the first and second data retention portions. The written data voltages where the threshold voltages of the transistors are canceled can be read by precharging and then discharging the first wiring.