FinFET Fin Formation Using Selective Patterned Layer Removal
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Solution Overview
Problem
The increasing complexity in forming FinFETs with varying sizes and pitches in ultra-large-scale integrated circuits leads to inconsistent fin sizes and etching rates, affecting the performance of semiconductor structures due to the difficulty in managing small spacings between fins and the damage caused by over-etching.
Innovation Solution
A method where the second patterned layer is removed before forming the first and third fins, using the first and third patterned layers as etching masks to create fins with larger spacings, thereby improving the morphology and performance of the semiconductor structure by avoiding additional fin formation and damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple patterned layers are maintained during etching to form fins with varying sizes and pitches, then the circuit density and integration scale are improved, but the manufacturing precision deteriorates due to inconsistent fin sizes and etching rates
Solution Approach 1:
The substrate is divided into multiple regions (first region, second regions, third regions) with different patterned layers, allowing independent etching control for fins of varying sizes and pitches while maintaining overall manufacturing precision
Solution Approach 2:
The second patterned layers are removed before the etching process to prevent them from interfering with the etching of fins in adjacent regions, ensuring uniform fin sizes and consistent etching rates across different circuit density areas
2Productivity
If the spacing between fins is reduced to increase circuit density, then the productivity is improved, but the manufacturing precision deteriorates due to difficulty in managing small spacings and over-etching damage
Solution Approach 1:
The second patterned layers are removed in advance before etching to eliminate potential over-etching damage to adjacent fins, enabling precise control of small spacings between fins while maintaining high circuit density
Solution Approach 2:
The first and third patterned layers serve as etching masks that mediate the etching process, protecting the fins from over-etching while allowing precise formation of fins with small spacings required for high circuit density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the patterning process, ensures uniformity in fin sizes and pitches, and enhances the performance of semiconductor structures by maintaining desired morphologies and reducing damage to the base substrate and fins.
Implementation Method 1
etching the substrate using the at least one first patterned layer and the at least one third patterned layer as an etching mask to form a base substrate, at least one first fin on the base substrate and at least one third fin on the base substrate
Data Source
AI summary
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a substrate having a first region, second regions and third regions; and forming a patterned structure on the substrate. The patterned structure includes at least one first patterned layer on the first region, at least one second patterned layer on the second region and at least one third patterned layer on the third region, the at least one first patterned layer is discrete from the at least one second region and the at least one second region is discrete from the at least one third region. The method also includes removing the second patterned layer; and etching the substrate using the first patterned layer and the third patterned layer as an etching mask to form a base substrate, the first fin on the base substrate and the third fin on the base substrate.