FinFET Cloak-Shaped Active Region Leakage Control
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Solution Overview
Problem
Conventional planar transistors face challenges in controlling the channel region due to short channel leakage effects, especially as semiconductor devices are scaled into deep sub-30 nanometer dimensions, leading to increased leakage current.
Innovation Solution
The implementation of fin field effect transistors (FinFETs) with a cloak-shaped active region and a gate structure that wraps around three sides, enhancing control over the channel region and reducing leakage current by using a silicon germanium epitaxial layer grown in a cloak-shaped recess, followed by a chemical mechanical polishing process to achieve a planar surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used with reduced minimum feature size to increase integration density, then more components can be integrated into a given area, but leakage current increases due to short channel leakage effects
Solution Approach 1:
The patent transitions from conventional planar transistors to FinFETs by adding a vertical dimension. The active region protrudes upward from the substrate surface forming a fin structure, and the gate wraps around three sides of this fin, creating a 3D configuration that enhances gate control over the channel while maintaining scaled dimensions.
Solution Approach 2:
The gate structure is configured to wrap around three sides of the active region fin, creating a nested configuration where the gate encloses the channel region. This wrapping structure provides superior electrostatic control compared to planar gates, effectively suppressing short channel leakage effects at scaled dimensions.
2Length of moving object
If semiconductor devices are scaled into deep sub-30 nanometer dimensions to continue shrinking, then device density increases, but the gate cannot fully control the channel region leading to increased leakage current
Solution Approach 1:
By transitioning to a vertical fin structure with a wrapping gate, the patent achieves effective gate control at deep sub-30 nanometer dimensions. The three-sided gate enclosure provides enhanced electrostatic control that overcomes the short channel effects that plague planar transistors at these scaled dimensions.
Solution Approach 2:
The patent employs a silicon germanium epitaxial layer for the active region, combining silicon and germanium materials. This composite material approach allows for precise control of carrier concentration and channel properties, enabling effective device operation at scaled dimensions while maintaining gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
FinFETs effectively reduce short channel leakage effects, allowing for better control of the channel region and minimizing leakage current, even at smaller dimensions, thereby improving the performance of semiconductor devices.
Implementation Method 1
a silicon germanium epitaxial layer grown in a cloak-shaped recess
Implementation Method 2
followed by a chemical mechanical polishing process to achieve a planar surface
Data Source
AI summary
A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.