MIM Capacitor High-k Film Liftoff Process
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Solution Overview
Problem
The challenge lies in manufacturing semiconductor devices with high-dielectric-constant films of MIM capacitors, where the high-k material with a dielectric constant of 10 or more is difficult to etch and easily separable from electrodes, leading to increased parasitic capacitance and wiring delays, especially when formed using sputtering methods.
Innovation Solution
A method involving the formation of a lower electrode, application of a photoresist, creation of an opening for a high-dielectric constant film, liftoff to isolate the film from the peripheral area, and subsequent deposition of a CVD insulating film to enhance adhesion and prevent separation, with specific film thickness ratios to optimize capacitance and withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a high-dielectric-constant film constituted of a high-k material having a dielectric constant of 10 or more is used as a dielectric film for an MIM capacitor, then the capacitance of the MIM capacitor is increased, but it becomes difficult to remove the high-dielectric-constant film formed in places where transistors or wirings are formed, resulting in increased parasitic capacitance or wiring delay
Solution Approach 1:
The patent divides the dielectric film formation process into two distinct layers: a lower dielectric film formed by CVD that covers the entire substrate including transistor regions, and an upper high-dielectric-constant film formed by sputtering that is selectively removed from transistor regions through liftoff. This segmentation allows each layer to serve different functions - the CVD layer provides easy removal capability while the sputtered layer provides high capacitance where needed
Solution Approach 2:
The patent extracts the high-dielectric-constant film from the transistor regions by forming an opening in the photoresist over the transistor area and performing liftoff to remove the sputtered high-k material from those regions. This extraction eliminates the harmful parasitic capacitance while preserving the beneficial high capacitance in the capacitor region
2Ease of manufacture
If a high-dielectric-constant film is formed by sputtering, then the film can be deposited, but the adhesion between the high-dielectric-constant film and the lower electrode is weaker, making the film easily separable
Solution Approach 1:
The patent creates a composite dielectric structure combining two different materials: a CVD-formed lower dielectric film with strong adhesion properties and a sputtered upper high-dielectric-constant film with high capacitance. The CVD layer acts as an adhesive base that prevents separation, while the sputtered layer provides the desired electrical properties
3Quantity of substance
If an upper electrode is formed on a high-dielectric-constant film, then the MIM capacitor structure is completed, but the upper electrode is separable more easily compared to being formed on a CVD insulating film
Solution Approach 1:
The composite dielectric structure with the CVD lower dielectric film provides a strong adhesion interface for the upper electrode. The upper electrode is formed on the sputtered high-k film which sits on the CVD layer, creating a hierarchical adhesion structure where the CVD layer ensures mechanical stability while the sputtered layer provides electrical performance
4Quantity of substance
If the high-dielectric-constant film is formed in places where transistors are formed, then the capacitance is increased, but the parasitic capacitance of the transistor is increased
Solution Approach 1:
The patent applies different dielectric film properties to different locations: the sputtered high-dielectric-constant film is present only in the MIM capacitor region where high capacitance is desired, while the transistor regions have only the CVD dielectric film with lower dielectric constant. This local differentiation eliminates parasitic capacitance in transistor areas while maintaining high capacitance in the capacitor area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the easy manufacture of semiconductor devices without high-dielectric-constant films in transistor or wiring areas, preventing separation and reducing parasitic capacitance while increasing the capacitance and withstand voltage of MIM capacitors.
Implementation Method 1
applying a photoresist on the lower electrode
Implementation Method 2
forming a CVD insulating film
Implementation Method 3
high-dielectric constant film constituted of a high-k material having a dielectric constant of 10 or more
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a lower electrode on a semiconductor substrate, applying a photoresist on the lower electrode, forming an opening in the photoresist spaced from the periphery of the lower electrode, forming a high-dielectric constant film of a high-k material having a dielectric constant of 10 or more, performing liftoff so that the high-dielectric-constant film remains on the lower electrode, and forming an upper electrode on the high-dielectric-constant film remaining after the liftoff.