CFET Wrap-Around Contacts for Independent Source/Drain Epitaxy
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling beyond 7 nm nodes due to difficulties in independently growing nFET and pFET source/drain epitaxy while maintaining vertical integration and electrical disconnection, particularly in forming wrap-around contacts for complementary FETs (CFETs).
Innovation Solution
The method involves forming stacked IC structures with CFETs that include wrap-around contacts, where a first FET is grown on a substrate with a spacer layer, and a second FET is vertically stacked above it, with conductive metal regions extending laterally and vertically to create electrical isolation and increased contact area, allowing for independent growth and electrical disconnection of nFET and pFET source/drain epitaxy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional nanowire/nanosheet source/drain epitaxy process is used for CFETs, then vertical integration is maintained, but it forms superposed n-doped epitaxy and p-doped epitaxy making it challenging to form independent n- and p-contacts and especially difficult for wrap-around contacts
Solution Approach 1:
The source/drain regions are segmented into separate n-doped and p-doped regions through selective epitaxial growth. The method uses separate epitaxial growth steps for n-type and p-type source/drain regions, allowing independent doping and contact formation for each type, thereby resolving the challenge of forming independent contacts in CFET structures.
Solution Approach 2:
Different doping types (n-type and p-type) are applied to different spatial locations within the source/drain regions. The epitaxial growth process selectively dopes specific regions with appropriate carrier types, enabling local optimization of electrical properties for nFET and pFET contacts while maintaining vertical integration.
2Reliability
If contact area is increased to reduce contact resistance, then source/drain contact resistance is improved, but transistor gate pitch scaling is constrained
Solution Approach 1:
The contact structure transitions from a planar two-dimensional contact to a three-dimensional wrap-around contact that extends laterally beneath the gate and vertically through the source/drain regions. This dimensional change allows the contact area to be increased without consuming additional gate pitch space, as the contact wraps around the source/drain structure in the vertical and lateral dimensions.
Solution Approach 2:
The contact structure is nested within and around the source/drain regions, with the conductive material wrapping around the vertically stacked source/drain structures. This nesting approach allows the contact to access multiple source/drain regions through a single contact opening, effectively increasing the contact area while maintaining compact gate pitch dimensions.
3Reliability
If wrap-around contacts are formed to increase effective contact area, then contact resistance is reduced, but process complexity for maintaining electrical disconnection increases
Solution Approach 1:
Dielectric intermediary layers are introduced between the n-doped and p-doped source/drain regions at critical interfaces. These dielectric layers act as electrical isolators that prevent unwanted charge sharing and electrical connection between complementary FET types, while still allowing the wrap-around contact structure to provide low-resistance paths to the respective doped regions.
Data Source
AI summary
The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.