VDMOS JFET Integrated Device Self-Driving Gate
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Solution Overview
Problem
VDMOS devices require a secondary driving voltage on the gate in addition to the drain/source, limiting their application and functionality.
Innovation Solution
Integration of a VDMOS and a JFET into a unitary structure, allowing the VDMOS to be self-driven without a secondary voltage by utilizing shared electrodes and doping regions, enabling current flow through a semiconductor channel that can be pinched off electronically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a VDMOS is used with a gate electrode requiring secondary driving voltage, then the device can control current flow between source and drain, but the device complexity increases and the application scope is limited
Solution Approach 1:
The patent combines a VDMOS and a JFET into a single integrated semiconductor device where the VDMOS gate electrode and JFET gate electrode are merged into a shared gate structure. This merging eliminates the need for separate gate control circuits, reduces device complexity, and enables the VDMOS to be self-driven by the JFET's current-controlled mechanism, thereby expanding application scope.
Solution Approach 2:
The integrated device achieves multi-functionality by combining the voltage-controlled characteristics of VDMOS with the current-controlled characteristics of JFET. The shared gate electrode allows the device to function both as a voltage-controlled switch (VDMOS mode) and as a current-controlled device (JFET mode), making it universally applicable in various circuit configurations without requiring additional external control circuits.
2Volume of moving object
If a VDMOS and JFET are integrated into a unitary structure, then the device size is reduced and self-driving capability is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The integrated device is segmented into distinct functional regions: a VDMOS region with its source, drain, and gate structures, and a JFET region with its own source, drain, and gate structures. The segmentation allows each transistor type to be manufactured using optimized process steps while maintaining close integration. The shared gate electrode is formed as a separate segment that electrically connects to both gate terminals, enabling compact layout without excessive manufacturing complexity.
3Device complexity
If shared electrodes and doping regions are used for integration, then the device complexity is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The doping regions are designed with local quality variations: the VDMOS doping regions (first and second doping regions) have specific depth and concentration profiles optimized for VDMOS operation, while the JFET doping regions (third and fourth doping regions) have different profiles optimized for JFET operation. The shared gate electrode has localized doping characteristics that enable it to function as a gate for both transistor types. This local quality differentiation allows each region to be manufactured with precision tailored to its specific function, reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the VDMOS to operate without a secondary driving voltage, expanding its application and reducing the size of the semiconductor device while maintaining functionality.
Implementation Method 1
a voltage on an oxide-insulated gate can induce a conducting channel between the two other contacts called source and drain
Implementation Method 2
enabling current flow through a semiconductor channel that can be pinched off electronically
Data Source
AI summary
A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. The first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second source electrode of the JFET respectively.


