Asymmetric Glass Core Substrate Layer Count Optimization
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Solution Overview
Problem
Legacy semiconductor substrates with symmetric front and backside copper layers are inefficient, leading to underutilization of backside layers and impedance discontinuities, which degrade high-speed signaling performance and increase manufacturing costs due to unnecessary layer counts.
Innovation Solution
The use of glass core substrates with an asymmetric number of front and backside copper layers, allowing for more efficient signal routing and reduced overall package layer count through techniques like through glass vias and laser-assisted etching, enabling better utilization of metal layers and improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If symmetric front and backside copper layers are used, then manufacturing process is simplified, but backside layers are underutilized and impedance discontinuities occur
Solution Approach 1:
The patent applies asymmetry by configuring different numbers of copper layers on the front side versus the backside of the substrate. The front side has more copper layers to handle complex signal routing, while the back side has fewer layers optimized for power delivery and ground connections. This asymmetric configuration eliminates impedance discontinuities caused by symmetric designs and ensures optimal utilization of each layer according to its functional requirements.
2Adaptability or versatility
If more copper layers are added to meet routing requirements, then signal routing capability is improved, but manufacturing time and costs increase
Solution Approach 1:
The patent applies local quality by concentrating the majority of copper layers on the front side where complex signal routing is required, while using fewer layers on the back side for simpler power and ground connections. This localized optimization ensures that routing capability is enhanced only where needed, avoiding the addition of unnecessary layers that would increase manufacturing complexity and reduce throughput.
3Ease of manufacture
If symmetric layer configuration is used, then manufacturing is easier, but overall package layer count increases
Solution Approach 1:
The patent reduces overall package layer count by implementing an asymmetric configuration where the front side has more layers for routing and the back side has fewer layers for power and ground. This eliminates the need for matching symmetric layers on both sides, thereby reducing the total layer count while maintaining ease of manufacture through standardized processing techniques.
4Ease of manufacture
If backside layers are utilized symmetrically, then manufacturing is simplified, but electrical performance degrades due to parasitic capacitance
Solution Approach 1:
The patent extracts the problematic backside copper layers that cause parasitic capacitance and impedance discontinuities. By removing or reducing these layers on the back side and replacing them with optimized power and ground connections, the design eliminates the source of electrical performance degradation while maintaining manufacturing simplicity through standardized processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and costs, enhances electrical performance by eliminating impedance discontinuities and parasitic capacitance, and allows for more efficient signal routing, improving the overall efficiency and quality of semiconductor packaging.
Implementation Method 1
laser-assisted etching
Data Source
AI summary
Embodiments described herein may be related to apparatuses, processes, and techniques directed to glass core-based substrates with an asymmetric number of front and back-side copper layers. In embodiments, the front and/or backside copper layers may be referred to as stack ups or as buildup layers on the glass core substrate. Embodiments may allow lower overall substrate layer counts by allowing for more front side layers where the signal routing may typically be highest, without requiring a matching, or symmetric, number of backside copper layers. Other embodiments may be described and/or claimed.