Asymmetric JFET Source Depth for Low On-Resistance
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Solution Overview
Problem
Current semiconductor power amplifiers, particularly those using GaAs technologies, are costly due to the need for dedicated substrates and processing steps, which are not compatible with silicon-based CMOS technologies, leading to increased manufacturing costs and complexity.
Innovation Solution
An asymmetric junction field effect transistor (JFET) is developed with an extended source region depth below shallow trench isolation, reducing on-resistance and increasing on-current without degrading drain voltage or significantly increasing the gate voltage required for turning the JFET off, achieved through ion implantation and specific doping concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GaAs technology is used for high-end power amplifiers, then performance is improved, but manufacturing cost increases due to dedicated substrates and processing steps
Solution Approach 1:
The patent enables power amplifier functionality to be integrated into standard silicon-based CMOS substrates, making the substrate universal for both digital logic and power amplification applications. This eliminates the need for dedicated GaAs substrates and allows shared processing infrastructure, thereby reducing manufacturing costs while maintaining performance.
Solution Approach 2:
The invention modifies standard CMOS device parameters (such as well depth, doping concentrations, and device geometry) to enable high-voltage power amplifier operation on silicon substrates. By changing these parameters, the patent achieves GaAs-like performance on cost-effective silicon platforms.
2Power
If modified SiGe BiCMOS technology is used for middle-range power amplifiers, then power capabilities are improved, but manufacturing cost increases due to additional processing steps
Solution Approach 1:
The patent merges power amplifier device structures with standard CMOS fabrication processes by forming JFET devices within existing CMOS well structures. This integration combines the power handling capabilities of bipolar technologies with the manufacturing simplicity of CMOS, reducing device complexity and processing steps while maintaining power capabilities.
3Adaptability or versatility
If standard CMOS technology is modified to enable power amplifiers, then compatibility is improved, but manufacturing cost increases due to new processing steps
Solution Approach 1:
The patent applies local modifications to specific regions of the CMOS substrate (such as forming deep n-wells and p-wells with specific doping profiles in designated areas) to enable power amplifier functionality. These localized changes allow CMOS compatibility to be maintained in non-critical areas while introducing necessary modifications only where power devices are required, thereby minimizing overall manufacturing cost impact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The asymmetric JFET design enhances performance by reducing on-resistance and increasing on-current, thereby improving power amplification capabilities while maintaining high impedance ratios, thus addressing the cost and compatibility issues of existing technologies.
Implementation Method 1
By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region and extends below the shallow trench isolation
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff / Vpinch.