Semiconductor/Solid-State Device Manufacturing TRIZ Cases
- Semiconductor Photodetector Insulating Film Thickness Control
Protective resist prevents HF-based etchant thinning of insulating films during electrode plating, preserving low reflectivity and optical performance.
- Negative-tone Resist Pattern Formation Without Prebaking
A resist composition with a photobase generator and acid supply component forms patterns without prebaking.
- Borazine-Based Thin Film Formation for Semiconductor Devices
A borazine compound reaction gas supplies silicon, boron, carbon, and nitrogen simultaneously to form thin films on semiconductor substrates.
- High-Voltage Semiconductor Drift Device with Alternating Wells
Alternating shallow wells reduce lateral resistance near the drift well edge, enabling high breakdown voltage and low pinch-off voltage.
- Filling Cavities in Transistor Insulation Zones
Carbonaceous filling prevents dielectric consumption and eliminates residual voids that cause short-circuits in microelectronic components.
- Wafer Segmentation for Low-Profile Flexible ICs
Selective wafer segmentation via isotropic etching resolves the contradiction between device flexibility and manufacturing yield.
- Stationary Infrared Heating for Wafer Drying
Stationary infrared heating prevents pattern collapse by compensating for radial cooling gradients in rotating semiconductor wafers.
- High Lateral Voltage Isolation Structure via Dual Trench Fill
Segmenting the isolation region into concentric trenches reduces film stress and charging effects while enabling wider dielectric fills.
- Phase Change Layer Fabrication for Low Power Semiconductor Devices
Alloying elements lower the process temperature, enabling void-free filling of semiconductor openings while reducing power consumption.
- Substrate Processing Apparatus Module Selection for Film Quality
Dynamic module selection using process and quality data resolves the contradiction between fixed gas configurations and versatile film processing needs.
- High Resistivity SOI Substrate with He-N2 Co-implanted Charge Trapping Layer
A high resistivity silicon-on-insulator substrate uses helium and nitrogen co-implantation to form a charge trapping layer within the handle substrate.
- Asymmetric JFET Source Depth for Low On-Resistance
An asymmetric junction field effect transistor extends the source region depth below shallow trench isolation to reduce on-resistance.
- TiN Film Formation via Chlorine Substitution
Alternating TiCl4 and NH3 deposition with hydrogen substitution removes chlorine impurities to lower film resistance.
- Tunnel Insulating Film Segmentation for Low-Voltage Memory
Segmented tunnel insulating film with electron trapping sites assists charge carrier movement, reducing program voltage while restraining leakage current.
- LDMOS Composite Drift Region for High Breakdown Voltage
A composite drift region merges deep and shallow n-type layers to maximize source-to-drain breakdown voltage while minimizing on-state resistance.
- Semiconductor Mesa Doping Profile for Short Channel Effect Suppression
An intermediate doping region in a semiconductor mesa suppresses the short channel effect by controlling dopant diffusion while maintaining carrier injection.
- Organoplatinum CVD Raw Material for Low-Temperature Platinum Thin Films
Diimine-coordinated organoplatinum compound enables low-temperature chemical vapor deposition of pure platinum thin films.
- Partial Etching Liquid Replacement for Semiconductor Wafer Processing
A partial replacement pattern discharges and supplies set amounts of etching liquid to maintain silicon concentration during wafer processing.
- Vertical GaN Device with Trenches for Current Distribution
Vertical trenches in a gallium nitride device allow current to flow through the substrate, resolving non-uniform distribution and high resistance issues.
- Basic Aqueous Solution for Silicon Film Removal
A pattern-forming method uses a basic aqueous solution to remove silicon-containing films from substrates.
- Wafer Thinning via Laser Line Beam Interface Formation
Laser line beam forms internal interface at specific depth, eliminating mechanical stress and waste from traditional grinding.
- LED Chip Tunneling Junction and Indium-Doped Layer Voltage Reduction
Indium-doped AlGaN layer and tunneling junction reduce operation voltage and epitaxy stress in LED chips.
- GaN Film Growth on Patterned SOI Substrate
Patterned silicon sidewalls guide epitaxial GaN growth to reduce dislocation and cracking.
- Source Drain Region Formation Using Dual Barrier Thickness
Distinct barrier film thicknesses for PMOS and NMOS regions prevent channeling and recoil during ion implantation.
- Source Drain Trench Control via Sacrificial Mandrel Etching
Sacrificial mandrels define trench geometry to control critical dimensions during source and drain formation, resolving precision trade-offs.
- HEMT Barrier Layer Segmentation for Threshold Voltage Control
Segmenting the barrier layer into distinct portions traps charge and recombines carriers, achieving a threshold voltage of at least 2 V.
- Semiconductor Wafer Manufacturing Air Circulation Control
Segmented air circulation regions with independent motors resolve uneven cleaning bottlenecks, ensuring uniform flow and pressure across the process chamber.
- CPP-GMR Sensor Extended Pinned Layer Resistivity Control
A CPP-GMR sensor uses a spacer layer with increased resistivity in its rear portion to define an extended pinned layer geometry.
- Silicide Gate Sidewall Expansion Control via Negative Slope Etching
A gate fabrication method uses a negatively sloped silicide profile to manage sidewall oxidation during light processing steps.
- Metal-Containing EUV Resist Post-Treatment for Etch Selectivity
Post-exposure thermal and plasma treatments modify metal-containing photoresist material properties to enhance dry development performance.