Grating-Based Plugs for BEOL Line End Formation
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in patterning extremely small line ends with pitches around 70 nanometers or less, where current lithographic processes face limitations in resolution, overlay tolerances, and line end uniformity, leading to increased costs and potential inability to print features with even extreme ultraviolet scanners.
Innovation Solution
The use of grating-based plugs and cuts, where an underlying metal grating structure serves as a template to define line end locations with improved control and uniformity, reducing reliance on lithography alignment and incorporating a sacrificial grating pattern that is etched to form precise line ends, followed by metal fill processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern line ends, then the manufacturing process is simple, but the manufacturing precision deteriorates for pitches around 70 nanometers or less
Solution Approach 1:
The patterning process is divided into multiple steps: first forming a mandrel pattern, then using spacer deposition to create the final line end pattern. This segmentation allows each step to be optimized independently, achieving high precision for sub-70nm pitches while managing overall process complexity.
Solution Approach 2:
The mandrel structure is formed in advance as a template before the actual line end pattern is created. This preliminary action establishes precise positional references that guide subsequent spacer formation, ensuring accurate line end placement and dimensions.
2Length of moving object
If shrink technologies are applied to reduce critical dimensions, then the line end size decreases, but the line width roughness and critical dimension uniformity worsen
Solution Approach 1:
A spacer material acts as an intermediary between the mandrel pattern and the final line end structure. The spacer thickness, controlled by atomic layer deposition, precisely defines the line end critical dimension without the roughness and uniformity issues associated with direct lithographic shrinking.
Solution Approach 2:
The mechanical lithographic shrinking process is replaced with a chemical vapor deposition process for spacer formation. This substitution eliminates the optical proximity correction and line width roughness problems inherent in lithographic-based shrink technologies.
3Manufacturing precision
If multiple lithographic masks are used to print extremely small via pitches, then the resolution capability is maintained, but the device complexity and manufacturing cost increase
Solution Approach 1:
The mandrel pattern serves as a copy or template that defines the positions of line ends without requiring direct lithographic printing of the final pattern. This copying approach enables extreme pitch resolution by transferring the pattern through spacer formation rather than additional lithographic steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances dimensional control of line ends, reduces processing time, and improves electrical contact, enabling smaller feature sizes and higher product density while maintaining manufacturing yields and reliability.
Implementation Method 1
a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask
Implementation Method 2
A lithographic patterning mask is formed above the second patterned hardmask layer, the lithographic patterning mask having regions protecting selected line end locations for the ILD material layer
Implementation Method 3
Portions of the second patterned hardmask layer not protected by the regions of the lithographic patterning mask are removed
Data Source
AI summary
Grating based plugs and cuts for feature end formation for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a hardmask layer above an interlayer dielectric (ILD) material layer. A first patterned hardmask layer is formed above the hardmask layer. A second patterned hardmask layer is formed above the first patterned hardmask layer. A lithographic patterning mask is formed above the second patterned hardmask layer. Portions of the second patterned hardmask layer not protected by the regions of the lithographic patterning mask are removed to form a third patterned hardmask layer and then the lithographic patterning mask is removed. A combined pattern of the third patterned hardmask layer and the first patterned hardmask layer is transferred to the hardmask layer and to the ILD material layer.