TSV Manufacturing via Multi-Stage Planarization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 2D and 3D semiconductor packaging technologies face challenges with increased size and performance deterioration due to the need for longer wires and higher power consumption as more devices are integrated, which are addressed by introducing Through-Silicon Vias (TSV) for vertical interconnections.
Innovation Solution
A method for manufacturing TSVs involving a stack structure with a substrate, ILD layer, and dielectric stop layer, where planarization processes with varying polishing rates are used to control the thickness and uniformity of metal and insulator layers, allowing for precise formation of TSVs through multiple polishing stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 2D packaging technology is used to integrate more devices, then device integration is achieved, but wire length increases and power consumption increases
Solution Approach 1:
The patent transitions from 2D planar interconnection to 3D vertical interconnection by forming through-silicon vias that penetrate the substrate. This dimensional change allows devices to be connected vertically rather than through long horizontal wires, reducing wire length and power consumption while maintaining high device integration
2Productivity
If conventional 3D packaging technology is used to integrate more devices, then device integration is achieved, but die size increases and performance deteriorates
Solution Approach 1:
The patent employs 3D vertical stacking with TSV interconnections to integrate devices in the vertical dimension rather than expanding the die area horizontally. Multiple device layers are stacked vertically and connected through vias, achieving high integration density without increasing die footprint
3Manufacturing precision
If multi-stage planarization process with dielectric stop layer is used, then polishing uniformity is improved, but process complexity increases
Solution Approach 1:
The patent introduces a dielectric stop layer before the planarization process to pre-establish a reference plane. This preliminary structure enables controlled stopping of the CMP process at specific depths, ensuring uniform polishing across multiple stages while managing process complexity through systematic layer design
4Manufacturing precision
If varying polishing rates are used in planarization processes, then thickness control is improved, but process control difficulty increases
Solution Approach 1:
The patent uses a dielectric stop layer as an intermediary reference plane during CMP processes. This intermediate layer with known properties and controlled thickness enables precise thickness control of overlying metal and insulator layers by providing a consistent stopping point, simplifying process control despite varying polishing rates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the polishing uniformity and reliability of the TSV formation process, reducing circuit complexity, increasing device speed, and lowering power consumption by enabling more efficient vertical interconnections.
Implementation Method 1
a first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer
Data Source
AI summary
A method for manufacturing TSVs comprises following steps: A stack structure having a substrate, an ILD layer and a dielectric stop layer is provided, in which an opening penetrating through the ILD layer and the dialectic stop layer and further extending into the substrate is formed. After an insulator layer and a metal barrier are formed on the stack structure, a top metal layer is formed on the stack structure to fulfill the opening. A first planarization process stopping on the metal barrier is conducted, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer. A second planarization process stopping on the dielectric stop layer is conducted, wherein the second planarization process has a polishing rate for removing the insulator layer greater than that for removing the dielectric stop layer. The dielectric stop layer is than removed.