High-Voltage Semiconductor Drift Device with Alternating Wells
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Solution Overview
Problem
High-voltage semiconductor drift devices face challenges in achieving low on-resistance and pinch-off voltage due to high lateral resistance near the edge of the drift well, making it difficult to protect the well during high voltage conditions.
Innovation Solution
The method involves implanting deep and shallow wells of alternating electrical conductivity types in a semiconductor substrate, with specific arrangements of field plates and insulating regions to optimize doping concentration and depletion, allowing for efficient current delivery and high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a deep well is implanted with low net doping concentration, then the breakdown voltage is improved, but the lateral resistance becomes high near the edge of the drift well
Solution Approach 1:
The patent applies local quality by creating alternating shallow wells of first and second conductivity types at the periphery of the deep well. These shallow wells are strategically positioned to provide localized doping concentration enhancement only where needed at the drift well edge, rather than uniformly throughout the entire structure. This allows the bulk deep well to maintain low doping for high breakdown voltage while the peripheral regions have enhanced doping to reduce lateral resistance.
Solution Approach 2:
The patent implements nesting by placing shallow wells within or adjacent to the deep well structure. The shallow wells of alternating conductivity types are nested at the periphery of the deep well, creating a multi-layered doping structure where smaller doped regions are positioned within the context of the larger deep well, allowing simultaneous optimization of both breakdown voltage and lateral resistance characteristics.
2Object-affected harmful factors
If the doping concentration is increased to reduce lateral resistance, then the on-resistance is improved, but the pinch-off voltage increases
Solution Approach 1:
The alternating shallow wells create localized high-doping regions only at the periphery where lateral resistance needs to be reduced, while the central drift region maintains low doping concentration. This spatial differentiation allows the device to achieve low on-resistance through peripheral doping without increasing the pinch-off voltage, as the low-doping bulk region determines the pinch-off characteristics.
3Object-affected harmful factors
If shallow wells are implanted to reduce lateral resistance, then the conductivity is improved, but the device complexity increases
Solution Approach 1:
The patent segments the doping structure into distinct deep wells and shallow wells of alternating conductivity types. Rather than using a single complex continuously varying doping profile, the solution divides the doping into discrete, manufacturable implantation steps that create alternating n-type and p-type shallow wells, simplifying the fabrication process while achieving the desired electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the semiconductor drift device to effectively handle high voltages, achieving low pinch-off voltage and high breakdown voltage while maintaining efficient current delivery, with the shallow wells being precisely depleted to manage resistance and voltage requirements.
Implementation Method 1
implanting a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material
Implementation Method 2
By performing a diffusion of the implanted dopants, the deep well of the first type is formed as a continuous doped region with its doping concentration increasing towards the center
Data Source
AI summary
The method comprises implanting a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material, the deep well of the first type comprising a periphery, implanting a deep well or a plurality of deep wells of a second type of electrical conductivity opposite to the first type of electrical conductivity at the periphery of the deep well of the first type, implanting shallow wells of the first type of electrical conductivity at the periphery of the deep well of the first type, the shallow wells of the first type extending into the deep well of the first type; and implanting shallow wells of the second type of electrical conductivity adjacent to the deep well of the first type between the shallow wells of the first type of electrical conductivity.