Triac Semiconductor Device Gate Trigger Current Balance
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Solution Overview
Problem
The existing TRIAC semiconductor devices face challenges in reducing the unbalance of gate trigger currents among trigger modes while maintaining low on-voltage, due to the high concentration region (P++ region) affecting the internal transistors' DC current amplification factor.
Innovation Solution
A semiconductor device with specific conductivity type regions and impurity concentrations, including a P++ region with higher impurity concentration than the P+ region, but not in direct contact with the gate electrode, and a P++ region with higher impurity concentration than the P+ region, improving ohmic properties and reducing on-voltages without affecting the DC current amplification factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high concentration region (P++ region) is formed to reduce on-voltage, then the on-voltage is reduced, but the gate trigger current becomes unbalanced among trigger modes
Solution Approach 1:
The patent applies local quality by positioning P++ regions specifically at electrode contact areas while maintaining lower impurity concentration in the base region near the gate electrode. This localized high concentration improves ohmic contact and reduces on-voltage, while the lower concentration in the base region preserves balanced transistor operation across all trigger modes, eliminating gate trigger current unbalance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the imbalance in gate trigger currents among trigger modes and lowers on-voltages by enhancing the ohmic properties of the electrodes, while maintaining the DC current amplification factor, thus improving the device's performance.
Implementation Method 1
improving the ohmic property with the electrodes and reducing the on-voltage
Implementation Method 2
encourage a recombination of carriers and achieve an improvement of (dv/dt)c (a rate of an increase in critical off-state voltage during commutation)
Data Source
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AI summary
A semiconductor device includes: a first thyristor wherein a first region of a first conductivity type, a second region of a second conductivity type, a third region of the first conductivity type, a fourth region of the second conductivity type are joined sequentially from a first surface side to a second surface of a semiconductor substrate having the first surface and the second surface opposite to the first surface, and a current flows from a first electrode formed on the first surface while being electrically connected to the first region to a second electrode formed on the second surface while being electrically connected to the fourth region; a thyristor TY2 wherein the third region, the second region, the first region, and a fifth region of the second conductivity type formed in contact with the first surface while being included in the first region are joined sequentially from the second surface side to the front surface, and a current flows from the second electrode to the first electrode electrically connected to the fifth region; a sixth region of the second conductivity type formed in contact with the first surface while being included in the first region and apart from the fifth region; a gate electrode formed on the front surface while electrically connecting the first region and the sixth region; a seventh region of the first conductivity type with an impurity concentration higher than that of the first region, which is formed in contact with the first surface while being included in the first region and apart from the sixth region and being electrically connected to the fifth region by the first electrode; and an eighth region of the first conductivity type with an impurity concentration higher than that of the third region, which is formed in contact with the second surface side of the third region and the fourth region, and with the second surface, while being electrically connected to the fourth region by the second electrode.