GaN Semiconductor Device with High-Doped Thin P-Type Layer
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Solution Overview
Problem
The existing manufacturing processes for GaN-based semiconductor devices are complex due to the requirement of multiple layers and high impurity concentrations in the p-type semiconductor layer, which complicates the configuration and increases resistance and energy consumption.
Innovation Solution
A semiconductor device is developed using a p-type GaN layer with a p-type impurity concentration of 2 × 10^20 cm^-3 or more and a thickness of 30 nm or less, simplifying the configuration and manufacturing process by eliminating the need for additional p-type GaN layers, thereby reducing resistance and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple p-type GaN layers with high impurity concentrations are used, then the reverse breakdown voltage is improved, but the device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent applies parameter changes by precisely controlling the p-type impurity concentration within the range of 1×10^20 to 1×10^21 cm^-3 and optimizing the layer thickness to 30-200 nm. This parameter optimization enables a single layer to achieve both high reverse breakdown voltage (several hundred volts to 1000 V or more) and low forward resistance, eliminating the need for multiple layers with different impurity concentrations while maintaining reliable diode performance.
2Reliability
If multiple p-type GaN layers are used, then the reverse breakdown voltage is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent simplifies the manufacturing process by establishing specific parameter ranges for p-type impurity concentration (1×10^20 to 1×10^21 cm^-3) and layer thickness (30-200 nm). These optimized parameters enable a single p-type GaN layer to achieve the required reverse breakdown voltage of several hundred volts to 1000 V or more, eliminating the need for complex multi-layer fabrication processes while ensuring reliable device performance.
3Loss of energy
If the p-type GaN layer is made thinner, then the forward resistance is reduced, but the reverse breakdown voltage decreases
Solution Approach 1:
The patent resolves this contradiction by optimizing two parameters simultaneously: the p-type impurity concentration (1×10^20 to 1×10^21 cm^-3) and the layer thickness (30-200 nm). This dual parameter optimization creates a balance where the thin layer (30-200 nm) reduces forward resistance while the high impurity concentration maintains the depletion layer width necessary for achieving reverse breakdown voltages of several hundred volts to 1000 V or more.
Solution Approach 2:
The patent applies local quality by creating a highly doped region at the pn-junction interface within the p-type GaN layer. The localized high impurity concentration (1×10^20 to 1×10^21 cm^-3) in this specific region enables efficient charge carrier generation and transport, reducing forward resistance, while the overall layer structure maintains the electrical field distribution needed for high reverse breakdown voltage.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
A semiconductor device is included a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor, a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of 1 × 1020 cm-3 or more, a first electrode disposed in contact with the first semiconductor layer, and a second electrode disposed in contact with the second semiconductor layer, and the semiconductor device functions as a pn-junction diode.