Self-aligned trench over fin semiconductor structure
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Solution Overview
Problem
Semiconductor fins have limited lateral dimensions due to lithographic constraints, making it challenging to increase their surface area without reducing printed dimensions, which hampers applications like field effect transistors and capacitors.
Innovation Solution
A method involving a stack of hard mask portions and a dielectric material layer is used to form semiconductor fins with a trench, where the dielectric layer is etched anisotropically to create a mask, allowing for the patterning of semiconductor material into fins with increased surface area without altering lithographically printed dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If lithographically printed lateral dimensions are reduced to increase surface area, then surface area increases, but manufacturing precision and device performance deteriorate
Solution Approach 1:
The patent introduces a vertical dimension by forming a trench cavity within the semiconductor fin structure. This allows the fin to increase its effective surface area through vertical depth (the trench) rather than relying solely on lateral dimension reduction, thereby resolving the contradiction between surface area enhancement and manufacturing precision maintenance
Solution Approach 2:
The patent embeds a trench cavity within the semiconductor fin, creating a nested structure where the cavity is contained inside the fin body. This nesting approach increases the internal surface area available for device formation without altering the external lateral dimensions that are constrained by lithography
2Area of stationary object
If trench is formed to increase channel area, then channel area increases, but device complexity increases
Solution Approach 1:
The trench formation process is self-aligned to the semiconductor fin, using the fin structure itself as the alignment reference. This self-service approach increases channel area through the trench while minimizing additional complexity by eliminating the need for separate alignment steps and processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the creation of semiconductor fins with enhanced surface area, suitable for improved performance in devices like field effect transistors, by forming trenches that are self-aligned to the fins, thereby increasing the channel area without reducing the lateral dimensions.
Implementation Method 1
The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion
Implementation Method 2
The semiconductor material layer is patterned into a semiconductor fin by anisotropically etching the semiconductor material layer employing the dielectric material portion as an etch mask
Implementation Method 3
A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer
Implementation Method 4
The first hard mask portion is laterally recessed by an isotropic etch
Data Source
AI summary
A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery.