Top Via Misalignment Compensation via Dielectric Liners
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face reliability concerns due to misalignment issues during back-end-of-line (BEOL) processing, which affect the integrity of metallization layers and connections between transistors, leading to increased resistive-capacitive (RC) delay and reduced integrated circuit speed.
Innovation Solution
The method involves forming a top via on a conductive line with dielectric liners and additional dielectric layers, using materials with high breakdown voltage to compensate for misalignment, thereby enhancing the reliability of connections and reducing RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional alignment processes are used during BEOL processing, then manufacturing simplicity is maintained, but misalignment occurs between conductive lines and vias leading to reliability issues
Solution Approach 1:
The patent applies preliminary action by forming compensating dielectric structures (liners and additional dielectric layers) on the conductive line before via formation. These structures pre-compensate for expected misalignment, ensuring that even when lithographic misalignment occurs, the via remains properly positioned relative to the conductive line, thus improving connection reliability without requiring higher manufacturing precision
Solution Approach 2:
The patent changes the physical parameters of the dielectric material by selecting materials with different etch selectivities and forming structures at different heights. The compensating dielectric structures are formed with specific height differences that correspond to the expected misalignment amount, effectively using parameter changes to compensate for alignment errors and improve via-to-line connectivity
2Reliability
If misalignment compensation structures are added, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by forming compensating dielectric structures only in specific locations where misalignment compensation is needed, rather than modifying the entire device structure. The liners are formed only on exposed portions of the conductive line, and additional dielectric layers are added only in regions where via misalignment is anticipated, thus improving reliability while minimizing added complexity
Data Source
AI summary
A method for fabricating a semiconductor device to account for misalignment includes forming a top via on a first conductive line formed on a substrate, forming liners each using a first dielectric material, including forming first and second liners to a first height along sidewalls of the top via, forming dielectric layers, including forming first and second dielectric layers on the first conductive line to the first height and adjacent to the first and second liners, respectively, recessing the top via to a second height, and forming an additional dielectric layer on the recessed top via to the first height using a second dielectric material. The first and second dielectric materials are selected to compensate for potential misalignment between the first conductive line and the top via.