Source Drain Region Formation Using Dual Barrier Thickness
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Solution Overview
Problem
Existing methods face challenges in forming source/drain regions in semiconductor devices that are suitable for both PMOS and NMOS regions due to difficulties in achieving appropriate ion implant barrier insulation film thicknesses, leading to issues like channeling and recoil phenomena during ion implant processes.
Innovation Solution
A method involving the formation of first and second ion implant barrier insulation films with specific thicknesses and strip processes to expose and implant regions separately, using photoresist patterns and spacers to form PMOS and NMOS source/drain regions, preventing channeling and recoil phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same thickness ion implant barrier insulation films are formed on both PMOS and NMOS regions, then the fabrication process is simplified, but the source/drain region properties cannot be optimized for each transistor type
Solution Approach 1:
The patent applies local quality by forming a first ion implant barrier insulation film with a first thickness on the PMOS region and a second ion implant barrier insulation film with a second thickness on the NMOS region. This allows each region to have locally optimized properties: the PMOS region receives ions through a thicker barrier for controlled implantation, while the NMOS region uses a thinner barrier for different implantation characteristics, thereby optimizing source/drain properties for each transistor type independently.
2Productivity
If ion implantation is performed without region-specific barrier thickness control, then the process is faster, but channeling and recoil phenomena occur reducing implantation quality
Solution Approach 1:
The patent applies parameter changes by controlling the thickness of ion implant barrier insulation films as a critical parameter. By setting specific thickness ranges for the first barrier film on PMOS and second barrier film on NMOS, the patent optimizes ion implantation quality by preventing channeling and recoil phenomena while maintaining efficient production. The thickness parameters are carefully selected to balance implantation speed and quality for each region.
3Manufacturing precision
If different thickness ion implant barrier insulation films are formed on PMOS and NMOS regions, then region-specific source/drain optimization is achieved, but the fabrication process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into distinct PMOS and NMOS regions with separately optimized ion implant barrier insulation films. The first barrier film is formed specifically on the PMOS region with a first thickness, and the second barrier film is formed on the NMOS region with a second thickness. This segmentation allows independent optimization of each region's source/drain properties while managing fabrication complexity through systematic process design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of source/drain regions tailored to each region's properties, reducing channeling and recoil effects, and achieving shallow junctions and efficient ion implantation.
Implementation Method 1
The first ion implant barrier insulation film of the NMOS region is stripped to a predetermined thickness while the photoresist pattern is stripped by performing a strip process for stripping the photoresist pattern
Implementation Method 2
an ion implant process is performed to form NMOS source/drain regions in the semiconductor substrate in which the NMOS LDD regions are formed
Implementation Method 3
reducing channeling and recoil effects, and achieving shallow junctions and efficient ion implantation
Implementation Method 4
reducing channeling and recoil effects, and achieving shallow junctions and efficient ion implantation
Data Source
AI summary
A method of forming a source/drain region of a semiconductor device includes forming a photoresist pattern through which an NMOS region of a semiconductor substrate is exposed, and then performing an ion implant process to form NMOS LDD regions in the semiconductor substrate of the NMOS region. An ion implant process is performed to form PMOS pocket regions in a PMOS region of the semiconductor substrate. Spacers are formed on sidewalls of a PMOS gate electrode pattern and sidewalls of an NMOS gate electrode pattern, and an ion implant process is performed to form PMOS source/drain regions in the semiconductor substrate in which the PMOS pocket regions are formed. An ion implant process is performed to form NMOS source/drain regions in the semiconductor substrate in which the NMOS LDD regions are formed.