Epitaxial Seed Layer Thickness Control for Semiconductor Stress

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Solution Overview

Problem

In semiconductor devices with process nodes smaller than 28 nm, the uneven thickness of epitaxial seed layers in source and drain regions leads to reduced stress and performance due to differing crystal growth speeds, resulting in inadequate carrier diffusion blocking and increased leakage current.

Innovation Solution

An epitaxial growth process that involves forming an initial seed layer with a thicker bottom and thinner sidewalls, followed by etching to thin the bottom, allowing for a thicker main body layer that fills the grooves and enhances channel stress, thereby improving device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If epitaxial growth is performed in grooves with U-shaped structure, then embedded epitaxial layers are formed in source and drain regions, but the seed layer thickness becomes uneven (thick at bottom, thin at sidewalls) due to different crystal growth speeds, reducing stress and device performance

Engineering Contradiction:
Improveseed layer thickness uniformityVSAvoiddevice performance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The epitaxial growth process is divided into multiple stages: first forming an initial seed layer, then performing selective etching to remove excess material from groove bottoms, followed by additional epitaxial growth to form the main body layer and cover layer. This segmentation allows control over thickness distribution to achieve uniform sidewall thickness while maintaining adequate bottom thickness for stress.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An initial seed layer is formed first to establish a foundation for subsequent processing. This preliminary layer enables the selective etching step to precisely control the final seed layer thickness profile, ensuring proper thickness at sidewalls for carrier diffusion blocking while maintaining adequate bottom thickness.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the seed layer thickness at sidewalls is increased to block carrier diffusion, then leakage current is reduced, but the main body layer volume decreases, reducing stress and device performance

Engineering Contradiction:
Improveleakage current controlVSAvoidmain body layer volume
Core Design Contradiction:
ReliabilityVSVolume of stationary object

Solution Approach 1:

The seed layer is designed with spatially varying thickness: thicker at sidewalls to block carrier diffusion and reduce leakage, and thinner at groove bottoms to preserve volume for the main body layer. This local quality differentiation optimizes both leakage control and stress generation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The thickness parameter of the seed layer is optimized to specific ranges: sidewall thickness of 5-15 nm for effective carrier diffusion blocking, while bottom thickness is controlled to 15-30 nm to maintain adequate volume for the main body layer. These parameter changes balance leakage control with stress generation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The process ensures the sidewalls meet thickness specifications, increases the main body layer volume, reduces leakage current, and enhances electrical performance by effectively isolating the main body layer from channel carriers.

Implementation Method 1

forming an initial seed layer on the inner side surfaces of the grooves through an epitaxial growth process

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

forming an initial seed layer on the inner side surfaces of the grooves through an epitaxial growth process

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS11476114B2Epitaxial growth process for semiconductor device and semiconductor device comprising epitaxial layer formed by adopting the same
Publication Date: 2022.10.18 SHANGHAI HUALI INTEGRATED CIRCUIT CORP
  • US11476114B2 patent drawing
  • US11476114B2 patent drawing
  • US11476114B2 patent drawing

AI summary

An epitaxial growth process for a semiconductor device includes providing a semiconductor substrate, forming a plurality of Dummy Gate structures on the surface of the semiconductor substrate, and forming grooves in a self-aligned manner on both sides of the Dummy Gate structures; forming an initial seed layer on the inner side surfaces of the grooves, the thickness of the formed initial seed layer on the bottoms of the grooves being greater and the thickness of the formed initial seed layer on the sidewalls being smaller since the growth speed of crystal faces <100> and <110> is different; longitudinally etching the initial seed layer to thin the bottom of the initial seed layer to form a seed layer; forming a main body layer on the seed layer, the main body layer filling the grooves; and forming a cover layer on the main body layer.