Silicon-filled Trench Voids via Liner and Annealing

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Solution Overview

Problem

Existing semiconductor processing methods often result in silicon-filled openings with voids due to uneven deposition, which can adversely affect electronic devices.

Innovation Solution

A method involving depositing an amorphous silicon film at a substrate with a trench, exposing it to an oxidizing or n-type dopant gas, and then annealing at a controlled temperature to crystallize the silicon while using a silicon mobility inhibitor to reduce voids without surface roughening.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If silicon is deposited at a higher rate at the top of the opening, then deposition speed is improved, but voids form in the interior of the opening

Engineering Contradiction:
Improvedeposition speedVSAvoiduniformity of fill
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A liner layer is deposited beforehand on the opening surfaces before the main silicon fill deposition. This liner layer modifies the deposition dynamics by providing a controlled interface that promotes more uniform silicon growth, preventing the top closure effect that causes voids while maintaining overall deposition efficiency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The deposition process uses parameter changes including temperature gradients and gas flow control to regulate silicon deposition rate. By adjusting these parameters, the process achieves uniform deposition throughout the opening depth, preventing void formation while maintaining acceptable deposition speed

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If the opening is closed at the top during deposition, then deposition time is reduced, but voids are trapped in the interior

Engineering Contradiction:
Improvedeposition timeVSAvoidquality of silicon fill
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The liner layer is formed in advance to control the deposition morphology from the start, preventing premature top closure that would trap voids. This preliminary structure enables continuous deposition without void entrapment

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The liner layer acts as an intermediary between the deposition environment and the silicon fill material. It mediates the deposition process by providing a controlled surface that promotes uniform growth and prevents void formation, allowing the opening to remain open longer during deposition

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces or eliminates voids in silicon-filled openings while maintaining a smooth surface, ensuring the silicon fill is crystallized and suitable for integrated circuit structures.

Implementation Method 1

exposing the deposited amorphous silicon film to an oxidizing gas

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

exposing the deposited amorphous silicon film to a nitriding gas

Methodology Applied
Scientific EffectNitriding: Nitriding

Implementation Method 3

exposing the deposited amorphous silicon film to an n-type dopant gas

Methodology Applied
Scientific EffectDoping: Dopants

Implementation Method 4

The substrate is then maintained at the anneal temperature to crystallize the amorphous silicon film in the trench

Methodology Applied
Scientific EffectCrystallization: Crystallisation

Implementation Method 5

The substrate is subsequently heated to an anneal temperature. The substrate is then maintained at the anneal temperature to crystallize the amorphous silicon film

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentEP2975635B1Process for forming silicon-filled openings with a reduced occurrence of voids
Publication Date: 2020.07.29 ASM IP HLDG BV
  • EP2975635B1 patent drawingFigure 1
  • EP2975635B1 patent drawingFigure 2
  • EP2975635B1 patent drawingFigure 3

AI summary

In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.