LDMOS Composite Drift Region for High Breakdown Voltage
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Solution Overview
Problem
Current high-power RF transistors, particularly LDMOS devices, face challenges in achieving high breakdown voltages while maintaining low on-state resistance and capacitance, which are essential for efficient operation at higher frequencies and power levels, due to the high costs associated with wide-bandgap semiconductors like gallium nitride.
Innovation Solution
The development of semiconductor devices with a deep n-type high voltage (NHV) region buried under the drain contact and extending towards the gate, combined with a composite drift region that merges a deep n-type NHV with a shallow NHV region, optimized to maximize source-to-drain breakdown voltage while minimizing drain current, on-state resistance, and capacitance, achieved through multiple epitaxy steps and anneal cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wide-bandgap semiconductors (e.g., gallium nitride) are used for high-power RF transistors, then breakdown voltage and power handling capability are improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent changes the doping parameters in the drift region by introducing a deep n-type high voltage (NHV) region with specific doping concentrations and depth profiles. This modifies the electrical characteristics to achieve high breakdown voltage (>200V, up to 300V) using conventional silicon-based materials instead of expensive wide-bandgap semiconductors.
Solution Approach 2:
The patent creates a composite drift region structure that merges a deep n-type NHV region with a shallow NHV region. This composite structure combines the advantages of deep doping (high breakdown voltage) with shallow doping (low on-state resistance), achieving high-power RF performance without using wide-bandgap materials.
2Reliability
If the drift region is optimized for high breakdown voltage, then voltage tolerance is improved, but on-state resistance increases
Solution Approach 1:
The patent segments the drift region into two distinct parts: a deep n-type NHV region extending from the surface to a first depth with lower doping concentration for high breakdown voltage, and a shallow NHV region extending from the surface to a second depth (greater than the first depth) with higher doping concentration for low on-state resistance. This segmentation allows each region to optimize for its specific function.
Solution Approach 2:
The patent applies different doping concentrations and depths at different locations within the drift region. The deep NHV region provides high voltage tolerance where needed, while the shallow NHV region provides low resistance pathways for current flow, achieving both high breakdown voltage and low on-state resistance simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables LDMOS devices to operate effectively at breakdown voltages above 200V, up to 300V, with reduced capacitance and on-state resistance, enhancing current capability and robustness, thus addressing the cost and performance limitations of existing wide-bandgap semiconductor-based RF transistors.
Implementation Method 1
achieved through multiple epitaxy steps and anneal cycles
Implementation Method 2
achieved through multiple epitaxy steps and anneal cycles
Implementation Method 3
charge carriers drift through a drift space between a channel region and the drain electrode under the electric field arising from an operating voltage applied between the source and drain electrodes
Data Source
AI summary
Semiconductor devices include a semiconductor substrate containing a source region and a drain region, a gate structure supported by the semiconductor substrate between the source region and the drain region, a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range, and a well region in the semiconductor substrate. The well region has a second conductivity type and is configured to form a channel therein under the gate structure during operation. Methods for the fabrication of semiconductor devices are described.