LED Chip Tunneling Junction and Indium-Doped Layer Voltage Reduction

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Solution Overview

Problem

Conventional LED chips face issues with high operation voltage due to lattice mismatch and high resistance in the p-type doped semiconductor layer, leading to increased stress during epitaxy and higher voltage requirements.

Innovation Solution

The implementation of an Indium-doped AlxGa1-xN based material layer and a tunneling junction layer between the doped semiconductor layers reduces lattice mismatch and voltage drop, while an undoped AlxGa1-xN based material layer minimizes leakage current, resulting in a low operation voltage and planar surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional LED structure with p-type doped semiconductor layer is used, then light emission function is achieved, but operation voltage becomes high due to high resistance and voltage drop

Engineering Contradiction:

Improveoperation voltageVSAvoidelectrical performance

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

An undoped AlxGa1-xN based material layer is introduced as an intermediary layer between the p-type doped semiconductor layer and the light emitting layer. This intermediary layer has lower resistance than the p-type layer, reducing the voltage drop at the junction and thereby lowering the overall operation voltage of the LED while maintaining electrical performance.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the doping parameter by introducing an undoped region (zero doping concentration) between the doped regions. This parameter change in the electrical properties of the intermediate layer reduces the overall resistance and voltage drop, achieving lower operation voltage.

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If epitaxy process is performed on material layers with lattice mismatch, then LED structure is formed, but stress is generated during epitaxy causing quality deterioration

Engineering Contradiction:

Improveepitaxy processVSAvoidepitaxy quality

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The composition parameter x in AlxGa1-xN is optimized to reduce lattice mismatch between adjacent layers. By adjusting the aluminum content, the lattice constant is tuned to minimize stress during epitaxy, improving both manufacturability and epitaxy quality.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If Indium-doped AlxGa1-xN based material layer is added to improve surface planarity, then surface quality is enhanced, but device complexity increases

Engineering Contradiction:

Improvesurface planarityVSAvoidlayer structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

Indium is doped locally in specific AlxGa1-xN layers to improve surface planarity where it is most needed, while other layers maintain their original composition. This localized modification achieves surface quality enhancement without requiring complete restructuring of the entire device.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the operation voltage and leakage current, enhancing the quality and performance of the LED chip by alleviating epitaxy stress and improving surface planarity.

Implementation Method 1

a tunneling junction layer, wherein the tunneling junction layer is disposed between the Indium-doped AlxGa1-xN based material layer and the first type doped semiconductor layer and/or disposed between the Indium-doped AlxGa1-xN based material layer and the second type doped semiconductor layer

Methodology Applied

Scientific EffectQuantum tunneling:

Implementation Method 2

Generally, there is lattice mismatch between each of the above material layers, which may cause the quality of the epitaxy to deteriorate due to the relatively large stress generated during the process of epitaxy

Methodology Applied

Scientific EffectLattice mismatch:

Implementation Method 3

an undoped AlxGa1-xN based material layer (0≦x≤1), wherein the undoped AlxGa1-xN based material layer is disposed on at least one surface of the light emitting layer

Methodology Applied

Scientific EffectLeakage current: Electrical Resistance

Data Source

PatentUS7763902B2Light emitting diode chip

Publication Date: 2010.07.27 ENNOSTAR CORP

AI summary

A LED chip including a substrate, a first type doped semiconductor layer, a second type doped semiconductor layer, a light emitting layer, at least an Indium-doped AlxGa1-xN based material layer (0≦x<1) and at least a tunneling junction layer is provided. The first type doped semiconductor layer is disposed on the substrate, and the light emitting layer is disposed between the first type doped semiconductor layer and the second type doped semiconductor layer. The Indium-doped AlxGa1-xN based material layer is disposed on at least one surface of the light emitting layer, and the tunneling junction layer is disposed between the Indium-doped AlxGa1-xN based material layer and the first type doped semiconductor layer and/or disposed between the Indium-doped AlxGa1-xN based material layer and the second type doped semiconductor layer, wherein the Indium-doped AlxGa1-xN based material layer and the tunneling junction layer are disposed on the same side of the light emitting layer.