Stress Transfer in Semiconductor Contact Layer Stacks
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Solution Overview
Problem
Conventional techniques for forming stressed dielectric layers in highly scaled transistor elements suffer from reduced efficiency due to limitations in deposition processes, leading to non-uniformities and defects that affect transistor performance and reliability.
Innovation Solution
The implementation of two or more individual stress-inducing layers with an interlayer dielectric material between them, using appropriate deposition techniques to achieve high conformal behavior and enhanced gap-filling capabilities, thereby reducing surface topography and improving the distribution and controllability of the stressed material during patterning and contact opening formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If a single highly stressed dielectric layer is deposited using PECVD techniques, then high intrinsic stress (up to 2 GPa compressive or 1 GPa tensile) can be achieved to enhance transistor performance, but deposition non-uniformities and surface topography defects occur that reduce manufacturing precision
Solution Approach 1:
The patent divides the single highly stressed dielectric layer into multiple separate stressed dielectric layers deposited at different times. Each layer is deposited using PECVD techniques to achieve high intrinsic stress, while the separation into multiple layers allows for better control of deposition uniformity and reduced surface topography defects compared to a single thick layer.
2Strength
If the thickness of the stressed dielectric layer is increased to provide more strain in the channel region, then transistor performance enhancement is improved, but deposition process non-uniformities and defects increase
Solution Approach 1:
Instead of depositing one thick stressed dielectric layer, the patent uses multiple thinner stressed layers. Each layer provides a portion of the required strain, and their combined effect achieves the desired total strain in the channel region while maintaining better deposition uniformity and reducing defects associated with thick single-layer deposition.
3Stress or pressure
If PECVD techniques are used to deposit highly stressed dielectric material, then high intrinsic stress can be achieved, but gap-filling capability is limited leading to surface topography issues
Solution Approach 1:
The patent segments the deposition process into multiple separate PECVD steps for depositing individual stressed layers. Each deposition step deals with a thinner layer, which improves gap-filling capability and reduces surface topography issues compared to depositing a single thick layer, while still achieving the required high intrinsic stress through the cumulative effect of multiple layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased deposition of highly stressed material above transistor elements, enhancing transistor performance and reducing defects and non-uniformities, particularly in densely packed device areas, while maintaining compatibility with existing process strategies.
Implementation Method 1
The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions
Implementation Method 2
forming a first stress-inducing layer above a first transistor formed above a substrate
Implementation Method 3
using appropriate deposition techniques to achieve high conformal behavior and enhanced gap-filling capabilities
Data Source
Figure 1a~1b
Figure 1c
Figure 2a~2b
AI summary
By forming two or more individual dielectric layers (230, 33OA, 233, 333, 234, 334) of high intrinsic stress levels with intermediate interlayer dielectric material (250A, 350A, 250B, 350B), the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element (220, 320A), even for highly scaled semiconductor devices (200, 300).