Asymmetric Memory Cell Structure for Threshold Voltage Stability
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Solution Overview
Problem
Conventional flash memory cells with two stacked gate structures experience performance degradation and short lifespan due to threshold voltage shifts after numerous operation cycles, leading to errors in binary data storage.
Innovation Solution
A memory cell structure with an asymmetric dual gate design, featuring heavily doped regions, lightly doped drain regions, and pocket doped regions with opposing dopant types, which reduces residual electrons and maintains threshold voltage stability even after thousands of programming/erasing cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional symmetric dual gate structure is used, then device complexity is reduced, but threshold voltage stability deteriorates after numerous operation cycles
Solution Approach 1:
The patent applies asymmetry by configuring different doped regions on either side of the dual gate structure. Specifically, a first doped region with first dopant is formed adjacent to the first gate structure, while a second doped region with second dopant (opposite conductivity type) is formed adjacent to the second gate structure. This asymmetric doping configuration compensates for charge trapping effects and maintains threshold voltage stability throughout the memory cell, resolving the contradiction between structural simplicity and voltage stability.
Solution Approach 2:
The patent implements local quality by introducing pocket doped regions with specific dopant types at localized positions within the substrate. These pocket doped regions are formed between the LDD regions and the heavily doped source/drain regions, with dopant types selected to locally compensate for charge trapping in specific areas. This localized doping strategy maintains threshold voltage stability without requiring complete structural redesign.
2Ease of manufacture
If conventional doped regions are used, then manufacturing process is simplified, but residual electrons accumulate causing performance degradation
Solution Approach 1:
The patent applies parameter changes by systematically varying dopant types and concentrations in different regions. The first doped region uses first dopant with first concentration, while the second doped region uses second dopant with second concentration. The pocket doped regions further modify local dopant parameters. These parameter variations create an asymmetric doping profile that actively compensates for charge trapping and prevents residual electron accumulation, maintaining performance over numerous operation cycles.
3Device complexity
If symmetric LDD regions are formed, then fabrication complexity is reduced, but threshold voltage shifts occur after programming/erasing cycles
Solution Approach 1:
The patent introduces asymmetry in the LDD region configuration by forming a first LDD region with first dopant adjacent to the first gate structure, and a second LDD region with second dopant (opposite conductivity type) adjacent to the second gate structure. This asymmetric LDD doping creates compensating electric fields that counteract threshold voltage shifts during programming and erasing operations, maintaining precise voltage control without requiring complete structural complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The asymmetric cell structure significantly reduces threshold voltage shifts and maintains accurate data storage across a large number of cycles, ensuring reliable binary data retention.
Implementation Method 1
A pocket doped region with a second type dopant is formed in the substrate overlapping with the first LDD region, wherein the second type dopant is opposite to the first type dopant in conductive type
Data Source
AI summary
A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.