Asymmetric Page Buffer Layout for Higher-Density 3D NAND
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Solution Overview
Problem
The increasing number of word lines in three-dimensional NAND flash memory devices limits the capacity of memory blocks due to the limited area of the row decoder, which in turn increases the size of the memory chip, making it difficult to achieve higher integration and capacity.
Innovation Solution
Implementing an asymmetric page buffer array architecture that redistributes the page buffer arrays and row decoder array to reduce the size of the memory chip while maintaining the number of stacked word lines, by burying the row decoder array under the word line step regions and dividing the page buffer arrays to accommodate the increased capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked word lines is increased to improve memory block capacity, then the storage capacity is improved, but the row decoder area must increase which is limited by the package length in the X direction
Solution Approach 1:
The patent transitions from a two-dimensional row decoder layout to a three-dimensional structure by placing the row decoder array in the vertical direction (Z-axis) beneath the word line step regions. This allows the row decoder to occupy the vertical space under the stacked word lines rather than requiring additional horizontal area, thereby enabling increased word line stacking without expanding the row decoder footprint in the X-Y plane.
Solution Approach 2:
The row decoder array is nested within the vertical space created by the stacked word line structure. Specifically, the row decoder is positioned in the peripheral circuit structure in the vertical direction below the word line step regions, effectively utilizing the vertical volume that would otherwise be unused. This nesting approach allows the row decoder to be integrated within the existing three-dimensional memory architecture without requiring additional chip area.
2Length of moving object
If the row decoder area is increased to support more stacked word lines, then the number of stacked word lines can increase, but the memory chip size increases
Solution Approach 1:
The patent utilizes the vertical dimension (Z-axis) to accommodate the row decoder array, transforming it from a planar component to a three-dimensional structure. By positioning the row decoder in the vertical direction below the word line step regions, the design enables support for more stacked word lines while maintaining the same horizontal chip footprint, thus increasing capacity without increasing chip size.
Solution Approach 2:
The patent employs an asymmetric page buffer array architecture where page buffers are divided into first and second arrays positioned at different locations. This dynamic and flexible layout allows optimization of the peripheral circuit structure to accommodate the vertically positioned row decoder, enabling the memory chip to support increased word line stacking while maintaining compact dimensions.
3Productivity
If the memory chip size is reduced for higher integration, then the integration density is improved, but the row decoder area becomes more limited
Solution Approach 1:
The patent resolves the area limitation by moving the row decoder array to the vertical dimension, positioning it beneath the word line step regions in the Z-axis direction. This three-dimensional placement allows the row decoder to occupy vertical space rather than horizontal space, enabling high integration density with compact chip size while still accommodating sufficient row decoder functionality for increased word line stacking.
Solution Approach 2:
The patent implements an asymmetric page buffer array architecture with first and second page buffer arrays positioned at different locations and configurations. This asymmetric design optimizes the peripheral circuit layout to accommodate the vertically positioned row decoder, allowing efficient use of available space and achieving high integration density without requiring symmetric or conventional layouts that would consume more area.
Data Source
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AI summary
Memory devices having an asymmetric page buffer array architecture are provided. The memory device includes a memory cell array in which each of plural memory planes is included in a cell array structure, and a row decoder array and a page buffer array included in a peripheral circuit structure vertically overlap the cell array structure. The row decoder array is buried in a region vertically overlapping a word line step region of the cell array structure and a partial region of a memory cell array adjacent to the word line step region. In the page buffer array, bit lines of a partial region of the memory cell array in which the row decoder array is buried are connected to a first page buffer array, and bit lines not included in the partial region are connected to a second page buffer array.