Asymmetric SONOS Memory Sidewall Charge Trapping
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Solution Overview
Problem
The existing non-volatile memory devices face challenges in improving programming and erasing speed, reducing operation voltage, and enhancing reliability, particularly with the SONOS structure, which is limited by the hot electron punch-through effect and drain-induced turn-on effect as the source-drain channel shrinks.
Innovation Solution
A non-volatile memory device with an asymmetric SONOS structure featuring a single charge trapping sidewall adjacent to the gate electrode, electrically isolated from the substrate and gate electrode, forming a non-straight angle, and using silicon nitride for the sidewall and silicon oxide for dielectric layers, which reduces charge trapping at other sides and allows normal read processes without increasing operation voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the source-drain channel length is shrunk to reduce device size, then the critical dimension is reduced, but hot electrons punch through along the select gate channel causing reliability degradation
Solution Approach 1:
The patent introduces an asymmetric charge trapping structure with a single charge trapping sidewall positioned only at one side of the gate electrode, creating an asymmetric electric field distribution. This asymmetry allows selective charge trapping that suppresses hot electron punch-through while maintaining small channel dimensions, directly resolving the contradiction between device miniaturization and reliability.
Solution Approach 2:
The charge trapping sidewall is locally positioned at a specific sidewall of the gate electrode rather than uniformly distributed. This local charge trapping mechanism creates a localized electric field that suppresses hot electron injection at critical regions while allowing the channel to remain short, thereby improving reliability without increasing device size.
2Ease of manufacture
If conventional SONOS structure is used to simplify manufacturing, then manufacturing complexity is reduced, but programming and erasing speed and reliability remain insufficient
Solution Approach 1:
The asymmetric charge trapping sidewall structure modifies the conventional symmetric SONOS architecture by introducing a single sidewall charge trapping layer at one side of the gate electrode. This asymmetric configuration enhances programming and erasing speeds through more efficient charge injection and extraction pathways while maintaining the relative manufacturing simplicity of the SONOS structure.
Solution Approach 2:
The patent transitions from a planar charge trapping approach to a three-dimensional sidewall charge trapping structure. The charge trapping sidewall extends vertically along the gate electrode sidewall, creating additional charge trapping capacity and improving P/E performance without significantly complicating the manufacturing process.
3Quantity of substance
If charge trapping is implemented at both sides of the gate electrode, then charge storage capacity is increased, but operation voltage increases and normal read processes cannot be performed
Solution Approach 1:
By implementing charge trapping at only one sidewall of the gate electrode rather than both sides, the patent achieves an asymmetric charge distribution that maintains sufficient charge storage capacity while avoiding the excessive voltage requirements that would result from symmetric dual-side charge trapping. The single sidewall configuration prevents voltage buildup that would interfere with normal read operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption, breakdown voltage, and electromagnetic interference, decreases source/drain doping concentration, and mitigates short channel and hot-carrier effects, enabling smaller critical dimensions and improved reliability.
Implementation Method 1
the single charge trapping sidewall is disposed adjacent to a sidewall of the gate electrode and electrically isolated from the substrate and the gate electrode
Implementation Method 2
a first dielectric layer used to electrically isolate the substrate from the gate electrode, and a second dielectric layer used to electrically isolate the gate electrode from the single charge trapping sidewall
Data Source
AI summary
A nonvolatile memory device comprises a substrate, a gate electrode, a single charge trapping sidewall and a source/drain region. The gate electrode is disposed on and electrically isolated from the substrate. The single charge trapping sidewall is disposed adjacent to a sidewall of the gate electrode and electrically isolated from the substrate and the gate electrode, so as to form a non-straight angle between the substrate and the single charge trapping sidewall. The source/drain region is disposed in the substrate and adjacent to the gate electrode.