Asymmetric Source/Drain Regions for Transistor Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the pitch of transistors in memory devices decreases, the probability of short channel effects (SCE) and capacitive coupling between adjacent transistors increases, while shallow source/drain regions reduce SCE but increase capacitive coupling, and deep regions decrease capacitive coupling but increase SCE and gate-induced drain leakage (GIDL).
Innovation Solution
Implementing asymmetric source/drain regions where the depth of one source/drain region is greater than the other, forming a junction that is directly coupled, allowing for both shallow and deep characteristics to be beneficially combined, reducing SCE and capacitive coupling while minimizing GIDL and drain-induced barrier lowering (DIBL).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If deep source/drain regions are used, then capacitive coupling between adjacent transistors is reduced, but short channel effects and gate-induced drain leakage increase
Solution Approach 1:
The source/drain structure is segmented into two distinct regions: a first source/drain region extending to a first depth and a second source/drain region extending to a second depth greater than the first depth. This segmentation allows each region to perform different functions - the shallower region reduces capacitive coupling while the deeper region controls short channel effects, thereby resolving the technical contradiction between reducing capacitive coupling and preventing short channel effects.
Solution Approach 2:
Different depths are assigned to different portions of the source/drain structure. The first source/drain region has a shallower depth optimized for reducing capacitive coupling between adjacent transistors, while the second source/drain region has a deeper depth optimized for controlling short channel effects and gate-induced drain leakage. This local differentiation of structural properties allows simultaneous optimization of multiple competing performance parameters.
2Quantity of substance
If transistor pitch is decreased, then memory device density is improved, but short channel effects and capacitive coupling increase
Solution Approach 1:
The segmented source/drain structure with dual depths enables effective control of short channel effects even when transistors are closely spaced. The deeper second source/drain region provides enhanced electrostatic control over the channel, allowing smaller transistor pitches to be implemented without suffering from increased short channel effects, thereby enabling higher memory device density.
Solution Approach 2:
The invention introduces a depth dimension differentiation within the source/drain structure. By varying the depth of different source/drain regions rather than using a uniform depth, the patent adds a dimensional degree of freedom that enables effective short channel control at reduced pitch, thus improving memory device density without compromising transistor performance.
3Quantity of substance
If transistor pitch is decreased, then memory device density is improved, but capacitive coupling between adjacent transistors increases
Solution Approach 1:
The segmented source/drain structure with the shallower first source/drain region specifically addresses capacitive coupling reduction. By having the first source/drain region extend to a shallower first depth, the structure reduces the overlapping electric fields between adjacent transistors, thereby reducing capacitive coupling even when pitch is decreased for higher density.
Solution Approach 2:
The local quality principle is applied by making the first source/drain region shallower than the second source/drain region. This localized depth differentiation specifically targets the reduction of capacitive coupling between adjacent transistors while maintaining the deeper second region for short channel control, enabling high-density layouts without excessive capacitive interference.
Data Source
AI summary
An example apparatus includes a first transistor and a second transistor, each having asymmetric source/drain regions. A source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor at a junction. A depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor.