Asymmetric Source Follower Doping for Higher Image Sensor Conversion Gain
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Solution Overview
Problem
Existing image sensor designs face challenges in achieving high dynamic range and conversion gain due to parasitic capacitance across metal oxide semiconductor field effect transistor junctions, which reduces charge collection capability.
Innovation Solution
Implementing a source follower transistor with an asymmetric doping profile, where a lightly doped drain region is adjacent only to the source region, reducing parasitic capacitance across the gate-drain junction and enhancing conversion gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a source follower transistor with conventional symmetric doping is used, then the transistor structure is simple and easy to manufacture, but parasitic capacitance across the gate-drain junction increases, reducing conversion gain
Solution Approach 1:
The patent applies asymmetry by implementing an asymmetric doping profile in the source follower transistor, where the drain region has a different doping concentration than the source region. Specifically, the drain is lightly doped compared to the source, which reduces the parasitic capacitance across the gate-drain junction. This asymmetric structure directly addresses the contradiction by sacrificing manufacturing simplicity to achieve higher conversion gain through reduced parasitic effects.
Solution Approach 2:
The patent applies local quality by modifying the doping concentration in specific regions of the transistor. The drain region is locally adjusted to have a lighter doping concentration compared to the source region, creating a non-uniform doping profile. This localized modification optimizes the electrical characteristics at critical junctions (gate-drain) without changing the entire transistor structure, thereby improving conversion gain while maintaining overall device functionality.
2Reliability
If parasitic capacitance is reduced to increase conversion gain, then charge collection capability improves, but transistor performance may deteriorate due to insufficient doping
Solution Approach 1:
The patent applies local quality by selectively doping different regions with different concentrations. The source region maintains high doping for good charge collection, while the drain region is lightly doped to reduce parasitic capacitance. This localized differentiation resolves the contradiction by optimizing each region's doping level for its specific function rather than using a uniform doping profile throughout the transistor.
Solution Approach 2:
The patent applies segmentation by dividing the transistor's doping structure into distinct zones with different doping characteristics. The source and drain regions are segmented with different doping concentrations, allowing independent optimization of charge collection (source) and parasitic capacitance reduction (drain). This segmentation enables simultaneous achievement of good charge collection capability and high conversion gain.
3Reliability
If a lightly doped drain region is added to reduce parasitic capacitance, then conversion gain increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies asymmetry by introducing a lightly doped drain region that breaks the symmetry of conventional transistors. This asymmetric doping profile (lightly doped drain vs. heavily doped source) directly reduces parasitic capacitance and increases conversion gain. The added complexity of asymmetric doping is justified by the significant improvement in conversion gain, making this a worthwhile trade-off for high-performance image sensors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The asymmetric doping profile increases conversion gain by minimizing parasitic capacitance, allowing for improved charge collection and higher dynamic range in image sensors.
Implementation Method 1
parasitic capacitance across the gate-drain junction of the transistor is decreased, which provides a higher conversion gain of the pixel
Implementation Method 2
Each pixel includes a photodetector as well as a circuit to collect the charge from the photodetector in response to a light input
Data Source
AI summary
An image sensor pixel array includes a source follower transistor configured with an asymmetric doping profile under its gate. In an example, a given pixel of a pixel array includes a photodetector coupled to a readout circuit, which includes a transfer gate between the photodetector and a source follower transistor. In an example, the source follower transistor includes doped source and drain regions with a lightly doped drain (LDD) region adjacent to the source region, but no corresponding LDD region adjacent to the drain region. Such a configuration allows for reduced parasitic capacitance across the gate-drain junction of the transistor, which provides a higher conversion gain for the pixel.