Radiation Controlled Devices TRIZ Cases

An insulation film encloses the transfer channel to block charge leakage to the ground region and improve transfer efficiency in small BSI pixels.

By isolating the floating diffusion node from second-die wiring, this stacked pixel structure boosts conversion gain, HDR, and resolution.

Dielectric etch stop regions limit excess BDTI trench depth at cross-road portions, protecting floating diffusion nodes in CMOS image sensors.

Metal grid extensions partially shield autofocus photodiodes inside the pixel array, enabling PDAF while reducing camera size and complexity.

Tungsten-filled deep trenches and bond pad connections enable CMOS-compatible SPAD fabrication while reducing crosstalk and gapfill issues.

Offset and tilted microlenses match local light incident angles, improving pixel focus alignment and photoelectric conversion efficiency.

An encapsulant-defined cavity and lid create a hermetic transceiver package that cuts size while improving reliability and signal performance.

A convex lens, optical spacer, and anti-reflection coatings redirect near-infrared light to the photodiode, boosting CMOS sensor sensitivity.

A landing-wiring mark pattern overlapping the through via helps verify via openness and improve image sensor interconnect reliability.

A central transfer-transistor pixel layout shortens charge paths to improve image sensor sensitivity, conversion gain, and noise performance.

Dual optical microstructures with different glass transition temperatures guide wide-angle light into CMOS pixels and reduce cross-talk.

Aligned side surfaces and a lateral connection path cut voltage-path resistance while protecting the photoelectric conversion film during fabrication.

Multi-layer trench dielectrics reflect stray light between adjacent pixels, improving quantum efficiency and reducing dark current.

A widened conductive layer above the transfer gate reduces via damage and preserves low-resistance connections as image sensor pixels shrink.

Separating the gate COF and gate connection FPCB onto different detector sides shrinks TFT X-ray detector size and reduces connector interference.

A two-direction bendable panel assembly conforms to pipe surfaces for stable, high-quality radiation imaging with reduced circuit interference.

A stacked pixel layout places dual charge storage units on the opposite substrate surface to raise saturation charge, sensitivity, and layout freedom.

Low-refractive index and light-blocking patterns separate adjacent color filters to cut pixel crosstalk and improve light reception and SNR.

Dual dielectric walls confine light in a thicker image sensor pixel, boosting quantum efficiency and low-light signal collection.

A vertical deep device isolation pattern limits pixel cross-talk, avoids bowing and voids, and preserves full well capacity in CMOS image sensors.

An asymmetric source follower doping profile cuts gate-drain parasitic capacitance, boosting pixel conversion gain and charge collection.

A split frontside-backside DTI layout isolates pixels while enabling defect-repair annealing that cuts dark current and leakage.

A single ARC deposition coats microlenses and bond pad trenches together, cutting image sensor pad-open-last process cost and steps.

Gallium doping limits out-diffusion in CMOS image sensor photodetectors, preserving full well capacity, isolation, and dynamic range.

Separate electron and hole readout paths extend dynamic range while avoiding the speed and power penalties of multiple exposures.

Dummy conductive members level stacked sensor bonding surfaces, improving substrate bondability and reducing cracks and gaps.

Frontside deep trench isolation enables deeper pixel barriers, cutting electron leakage, optical crosstalk, and dark current noise.

Deep trench isolation and tungsten-filled connections enable CMOS-compatible SPAD fabrication while reducing optical and electrical crosstalk.