Asymmetric Spacer Memory Cell for Faster Charge-Trap Programming
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Solution Overview
Problem
Conventional non-volatile memory cells with symmetric spacers face inefficiencies in carrier injection during program operations, limiting the effectiveness and speed of data storage processes.
Innovation Solution
The design of a memory cell with an asymmetric spacer, where the wider part of the spacer is positioned over the second channel, allowing for increased carrier injection into the charge-trapping layer, enhancing the program operation efficiency by increasing the ratio of injection channel length to total channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a symmetric spacer is used in the memory element, then the structure is simple and manufacturing is easier, but the carrier injection efficiency during program operations is reduced
Solution Approach 1:
The patent applies asymmetry by configuring the spacer with different widths at opposite sides of the gate structure. Specifically, the first spacer has a first width at a first side of the gate structure and a second width at a second side of the gate structure, where the first width is different from the second width. This asymmetric configuration optimizes carrier injection efficiency during program operations while maintaining manufacturing feasibility through standard deposition processes.
2Productivity
If the injection channel length is increased to improve carrier injection, then the program operation efficiency is improved, but the total channel length increases which may affect device density
Solution Approach 1:
The patent applies local quality by creating non-uniform spacer widths at different locations. The first spacer has a first width at a first side and a second width at a second side, where the widths differ. This local variation in spacer geometry selectively extends the injection channel length only where needed for optimal carrier injection, while keeping other channel portions compact to maintain device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the efficiency of program operations by allowing more carriers to be injected into the charge-trapping layer, reducing the time required for program operations and enhancing data storage capabilities.
Implementation Method 1
The silicon nitride layer 24 is used as a charge-trapping layer. When a program operation of the memory element 10 is performed, electrons are injected into the silicon nitride layer 24 near the drain side through the second channel 29
Implementation Method 2
electron-hole pairs are generated at the junction between the N well region 11 and the P+ drain doping region 14 and a so-called band-to-band hot electron injection (BBHE) effect occurs. Consequently, electrons are injected into the silicon nitride layer 24 near the drain side through the second channel 29
Data Source
AI summary
A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.