Asymmetric SRAM Compute-in-Memory Circuit for Faster Low-Power Logic
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Solution Overview
Problem
The increasing gap between processor and memory processing speeds under the Von Neumann architecture leads to a prominent memory access power consumption wall, resulting in limited data computing efficiency due to low storage speed and high storage power consumption.
Innovation Solution
A computing-in-memory circuit is introduced, featuring an SRAM memory cell array with asymmetrically configured inverters, a control circuit that processes input signals based on an operation mode control signal, and a readout circuit for storing logical operation results directly in the memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored and retrieved using conventional SRAM memory cells with symmetric inverters, then the memory can perform basic storage functions, but the storage speed is low and power consumption is high due to the Von Neumann architecture separation of processing and storage
Solution Approach 1:
The patent merges the storage function and computing function into a single SRAM memory cell by adding asymmetric inverter logic. The memory cell can both store data and perform logical operations (AND, OR, NAND, NOR) directly within the cell, eliminating the need to transfer data between separate processing and storage units. This combining of functions directly addresses the Von Neumann bottleneck by enabling compute-in-memory, thereby improving storage speed and reducing power consumption associated with data movement.
Solution Approach 2:
The patent introduces asymmetric inverter configuration within the SRAM memory cell, where one inverter has different threshold characteristics than the other. This asymmetry enables the memory cell to perform logical operations in addition to storage. The asymmetric design allows the cell to interpret differential voltages as logical inputs and produce logical outputs, transforming a simple storage device into a computing-capable memory element, thus improving both speed and energy efficiency.
2Productivity
If frequent data exchange occurs between processor and memory to handle increasing calculation amounts, then processing capability is maintained, but storage speed becomes a bottleneck and power consumption increases
Solution Approach 1:
The patent implements preliminary action by performing logical operations directly within the memory cell before data needs to be transferred to the processor. The asymmetric inverter configuration enables the memory cell to pre-process data by executing logical operations (AND, OR, NAND, NOR) in-place. This preliminary computation eliminates the need for multiple read-write cycles that would otherwise be required to implement logic operations, thereby reducing the writing cycle time and improving overall data computing efficiency.
3Productivity
If conventional symmetric SRAM memory cells are used, then the circuit design is simple and manufacturing is easier, but the data operation rates are limited and computing efficiency is low
Solution Approach 1:
The patent applies asymmetry by configuring the two inverters in the SRAM memory cell with different threshold characteristics. This asymmetric inverter design enables the memory cell to perform logical operations in addition to storage. While this increases device complexity slightly, it dramatically improves data operation rates by enabling compute-in-memory functionality, allowing the memory to actively process data rather than merely store it.
Solution Approach 2:
The asymmetric inverter configuration gives the SRAM memory cell multi-functionality, enabling it to perform both storage and various logical operations (AND, OR, NAND, NOR). This universal capability allows a single memory cell to replace what would otherwise require separate storage and processing components, thereby improving data operation rates without proportionally increasing overall system complexity.
Data Source
AI summary
The computing-in-memory circuit includes: an SRAM memory cell array including at least one memory cell connected between a first bit line and a second bit line, the memory cell includes a first inverter and a second inverter cross-coupled with each other, and the first inverter and the second inverter have an asymmetric configuration with respect to each other; a control circuit configured to: receive a first input signal, a second input signal and an operation mode control signal, process the first input signal and the second input signal according to operation mode control signal, so as to obtain a processed first input signal and a processed second input signal, and apply the processed first input signal and the processed second input signal to the first bit line and the second bit line, respectively; and a readout circuit configured to read out data stored in memory cell from the memory cell.