Asymmetric State Detection for Non-Volatile Storage Defects
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Solution Overview
Problem
Conventional techniques for detecting defects in non-volatile storage elements during programming are inefficient, often requiring numerous sensing operations and may miss certain types of defects, and are limited by the limited logic available on the memory device.
Innovation Solution
A method is introduced to detect defects by forming sub-groups of memory cells based on their threshold voltage states, comparing the distribution of cells across these sub-groups, and using a running total to efficiently identify imbalances, which can indicate defects such as broken word lines or shorts, while parallel processing and strategic sub-group formation help speed up the detection process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sensing operations are used to detect defects, then defect detection is performed, but numerous sensing operations are required and certain defects may be missed
Solution Approach 1:
The patent divides the memory array into multiple sub-arrays and further segments them into groups based on threshold voltage characteristics. This segmentation allows parallel processing of different sub-arrays, reducing the total number of sequential sensing operations while maintaining comprehensive defect coverage through systematic group comparison.
Solution Approach 2:
The patent performs preliminary classification of memory cells into groups based on their threshold voltage states before conducting defect detection. This preliminary action organizes the data structure in advance, enabling more efficient comparison operations and reducing the number of sensing cycles needed to identify defects.
2Manufacturing precision
If multiple verify operations are performed for each state in multi-state flash memory, then programming accuracy is improved, but programming time increases
Solution Approach 1:
The patent segments the verification process by dividing the memory array into multiple sub-arrays that can be verified in parallel. Instead of sequentially verifying all cells in a single array, multiple sub-arrays undergo verification simultaneously, reducing total programming time while maintaining the required verification thoroughness for each state.
Solution Approach 2:
The patent implements a tiered verification approach where critical threshold voltage ranges undergo more stringent verification while less critical ranges use streamlined verification. This partial action strategy applies full verification effort only where necessary, reducing overall programming time while maintaining programming accuracy for essential states.
Data Source
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AI summary
Techniques are disclosed herein for determining whether there is a defect that occurred as a result of programming non-volatile storage elements. Example defects include: broken word lines, control gate to substrate shorts, word line to word line shorts, double writes, etc. The memory cells may be programmed such that there will be a substantially even distribution of the memory cells in different data states. After programming, the memory cells are sensed at one or more reference levels. Two sub-groups of memory cells are strategically formed based on the sensing to enable detection of defects in a simple and efficient manner. The sub-groups may have a certain degree of separation of the data states to avoid missing a defect. The number of memory cells in one sub-group is compared with the other. If there is a significant imbalance between the two sub-groups, then a defect is detected.