Asymmetric Parallel Synchronous Rectifiers for Power Converter Efficiency
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Solution Overview
Problem
Existing power converter designs face a trade-off between high-load and light-load efficiency due to the use of parallel synchronous rectifiers, where gate loss dominates at light loads and conduction loss at full loads, and asymmetric FET modulation approaches do not effectively reduce overall system losses.
Innovation Solution
A synchronous rectifier circuit with actively controlled switches in parallel, where each switch receives a unique control signal from a controller, allowing for independent operation and asymmetric current-carrying capabilities, enabling efficient rectification across a wide load range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher voltage rating transistors are used to handle greater voltage stress in center-tap secondary winding configurations, then voltage stress is managed, but gate charge and on-resistance increase, requiring more parallel devices and worsening light-load efficiency
Solution Approach 1:
The rectifier circuit is divided into multiple parallel transistor branches with independent control. This segmentation allows the system to use only the necessary number of high-voltage transistors at any given time, reducing the total gate charge that must be charged and discharged at light load conditions while still maintaining the voltage stress handling capability when needed
Solution Approach 2:
The system changes the operating parameters by dynamically adjusting the number of active transistors based on load conditions. At light load, fewer high-voltage transistors are activated, effectively reducing the total gate charge and improving light-load efficiency while maintaining the ability to handle voltage stress when full load is present
2Ease of manufacture
If symmetric FETs are used in parallel with the same gate drive signal, then device matching is simplified, but light-load efficiency is limited because large die FETs cannot be efficiently operated at low current
Solution Approach 1:
The parallel FET configuration is segmented into independently controllable branches. This allows the system to activate only the necessary number of FETs at any given time, enabling large die FETs to operate efficiently across a wider current range by keeping them fully on when active rather than operating in a high-loss linear region at light load
Solution Approach 2:
The system dynamically adjusts which FETs are active based on load current. At light load, fewer FETs are activated, allowing the active FETs to operate at higher current densities where they are more efficient. This dynamic adjustment resolves the contradiction between ease of manufacture and light-load efficiency
Data Source
AI summary
A power converter includes an input power source, a synchronous rectifier and a controller. The synchronous rectifier includes a plurality of actively controlled switches coupled in parallel and configured to rectify current delivered from the input power source to a load. The controller is operable to issue a first control signal for driving a first one of the actively controlled switches and issue a second control signal for driving a second one of the actively controlled switches. The first control signal is a different control signal than the second control signal so that the first actively controlled switch is controllable separately from the second actively controlled switch. The first actively controlled switch has a higher current-carrying capacity than the second actively controlled switch.